Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment
2005 (English)In: 10th IEEE European Test Symposium ETS´05,2005, Tallinn, Estonia: IEEE Computer Society Press , 2005Conference paper (Refereed)
This paper addresses the energy minimization problem for system-on-chip testing. We assume a hybrid BIST test architecture where a combination of deterministic and pseudorandom test sequences is used. The objective of our proposed technique is to find the best ratio of these sequences so that the total energy is minimized and the memory requirements for the deterministic test set are met without sacrificing test quality. We propose two different heuristic algorithms and a fast estimation method that enables considerable reduction of the computation time. Experimental results have shown the efficiency of the approach for finding reduced energy solutions with low computational overhead.
Place, publisher, year, edition, pages
Tallinn, Estonia: IEEE Computer Society Press , 2005.
system-on-chip, testing, hybrid BIST, energy minimization, deterministic test sequence, pseudorandom test sequence
IdentifiersURN: urn:nbn:se:liu:diva-24568DOI: 10.1109/ETS.2005.16Local ID: 6737ISBN: 0-7695-2341-2OAI: oai:DiVA.org:liu-24568DiVA: diva2:244889
10th IEEE European Test Symposium ETS´05