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An Improved Estimation Technique for Hybrid BIST Test Set Generation
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Dept. Computer Engineering Tallinn University of Technology.
Dept. Computer Engineering Tallinn University of Technology.
2005 (English)In: IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems DDECS,2005, Sopron, Hungary: IEEE Computer Society Press , 2005, 182- p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an improved estimation technique for hybrid BIST test set generation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is determined by the ratio of those test patterns in the final test set. Unfortunately, exact algorithms for finding the optimal test sets are computationally very expensive. And several heuristics have been developed to address this problem based on estimation methods. In this paper we propose an improved estimation technique for fast generation of the hybrid test set. The technique is based on fault simulation results, and experiments have shown that the proposed technique is more accurate than the estimation methods proposed earlier.

Place, publisher, year, edition, pages
Sopron, Hungary: IEEE Computer Society Press , 2005. 182- p.
Keyword [en]
hybrid BIST, pseudorandom test pattern, deterministic test pattern, estimation technique
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-24569Local ID: 6738OAI: oai:DiVA.org:liu-24569DiVA: diva2:244890
Available from: 2009-10-07 Created: 2009-10-07

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http://www.ida.liu.se/labs/eslab/publications/pap/db/ddecs05.pdf

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Jervan, GertPeng, Zebo

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CiteExportLink to record
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Citation style
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