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Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
IDA Linköpings Universitet.
IC Design Digital Design and Test Philips Research Labs.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
IC Design Digital Design and Test Philips Research Labs.
2005 (English)In: IEEE European Test Symposium ETS 05,2005, Tallinn, Estonia: IEEE Computer Society Press , 2005Conference paper (Refereed)
Abstract [en]

Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module s manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC 02 SOC Test Benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction in the expected test application time, without any modification to the SOC or ATE.

Place, publisher, year, edition, pages
Tallinn, Estonia: IEEE Computer Society Press , 2005.
Keyword [en]
testing, systems-on-chip, yield-per-module, TAM, test scheduling
National Category
Computer Science
URN: urn:nbn:se:liu:diva-24699Local ID: 6939OAI: diva2:245021
Available from: 2009-10-07 Created: 2009-10-07

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Larsson, Erik
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The Institute of TechnologyESLAB - Embedded Systems Laboratory
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