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Low Complexity Hardware Interleaver for MIMO-OFDM based Wireless LAN
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2009 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, 2009, 1747-1750 p.Conference paper, Published paper (Refereed)
Abstract [en]

A low complexity hardware interleaver architecture is presented for MIMO-OFDM based Wireless LAN e.g. 802.11n. Novelty of the presented architecture is twofold; 1) Flexibility to choose interleaver implementation with different modulation scheme and different size for different spatial streams in a multi antenna system, 2) Complexity to compute on the fly interleaver address is reduce by using recursion and is supported by mathematical formulation. The proposed interleaver architecture is implemented on 65nm CMOS process and it consumes 0.035 mm2 area. The proposed architecture supports high speed communication with maximum throughput of 900 Mbps at a clock rate of 225 MHz.

Place, publisher, year, edition, pages
2009. 1747-1750 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-21902DOI: 10.1109/ISCAS.2009.5118113ISI: 000275929801117ISBN: 978-1-4244-3828-0 (print)ISBN: 978-1-4244-3827-3 (print)OAI: oai:DiVA.org:liu-21902DiVA: diva2:246008
Conference
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009; Taipei; Taiwan
Available from: 2009-10-08 Created: 2009-10-06 Last updated: 2014-09-08

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Asghar, RizwanLiu, Dake

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  • nn-NO
  • nn-NB
  • sv-SE
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