liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2009 (English)In: 12th EUROMICRO Conference on Digital System Design, 2009, 699-706 p.Conference paper, Published paper (Refereed)
Abstract [en]

HSPA evolution has raised the throughput requirements for WCDMA based systems where turbo code has been adapted to perform the error correction. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithm used in WCDMA based systems does not freely allows to use them due to high percentage of memory conflicts. This paper provides a comprehensive analysis for reduction of interleaver memory conflicts while generating more than one address in a single clock cycle. It also provides trade-off analysis in terms of area and power efficiency for multiple architectures for different functions involved in the interleaver design. The final architecture supports processing of two parallel SISO blocks and manages the conflicts by applying different approaches like stream misalignment, memory division and small FIFO buffer. The proposed architecture is low cost and consumes 4.3K gates at a frequency of 150MHz. This work also focuses on reduction of pre-processing overheads by introducing the segment based modulo computation, thus providing further relaxation to SISO decoding process.

Place, publisher, year, edition, pages
2009. 699-706 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-25596DOI: 10.1109/DSD.2009.178ISI: 000275715100094ISBN: 978-0-7695-3782-5 (print)OAI: oai:DiVA.org:liu-25596DiVA: diva2:246049
Conference
12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009; Patras; Greece
Available from: 2009-10-08 Created: 2009-10-08 Last updated: 2014-08-28

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Asghar, RizwanWu, DiEilert, JohanLiu, Dake

Search in DiVA

By author/editor
Asghar, RizwanWu, DiEilert, JohanLiu, Dake
By organisation
Computer EngineeringThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 327 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf