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An Approach to System-Level DFT
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Dep. of Computer Engineering Tallinn University of Technology.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2005 (English)In: System-level Test and Validation of Hardware/Software Systems / [ed] M. Sonza Reorda, Z. Peng, M. Violante, Berlin: Springer Berlin Heidelberg , 2005, 121-149 p.Chapter in book (Other academic)
Abstract [en]

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.

As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.

System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:

• modeling of bugs and defects;

• stimulus generation for validation and test purposes (including timing errors;

• design for testability.

For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.

Place, publisher, year, edition, pages
Berlin: Springer Berlin Heidelberg , 2005. 121-149 p.
Series
Springer Series in Advanced Microelectronics, 17
Keyword [en]
testing, design for testability
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-28489Local ID: 13637ISBN: 1-85233-899-7 (print)ISBN: 978-1-84628-145-7 (print)OAI: oai:DiVA.org:liu-28489DiVA: diva2:249299
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-09-27Bibliographically approved

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Jervan, GertPeng, ZeboEles, Petru Ion

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