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Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2005 (English)In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, 83- p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a combination of deterministic and pseudorandom test sequences is used, the power-constrained test scheduling problem can be formulated as an extension of the two-dimensional rectangular packing problem and a heuristic has been proposed to calculate the near optimal order of different test sequences. The method is also generalized for both test-per-clock and test-per-scan approaches. Experimental results have shown that the proposed heuristic is efficient to find a near optimal test schedule with a low computation overhead.

Place, publisher, year, edition, pages
Porto, Portugal: IEEE Computer Society Press , 2005. 83- p.
Keyword [en]
testing, power optimization, system-on-chip, built-in self-test, BIST, abort-on-fail
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-28507DOI: 10.1109/DSD.2005.63Local ID: 13656ISBN: 0-7695-2433-8 (print)OAI: oai:DiVA.org:liu-28507DiVA: diva2:249317
Conference
8th Euromicro Conference on Digital System Design DSD2005
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-08-16

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Publisher's full texthttp://www.ida.liu.se/labs/eslab/publications/pap/db/zhihe_dsd05.camera.pdf

Authority records BETA

He, ZhiyuanJervan, GertEles, Petru IonPeng, Zebo

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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  • Other style
More styles
Language
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Output format
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