Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
2005 (English)In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, 403- p.Conference paper (Refereed)
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM will shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.
Place, publisher, year, edition, pages
Porto, Portugal: IEEE Computer Society Press , 2005. 403- p.
testing, system-on-chip, test access mechanism, TAM, bus structure, test data transportation
IdentifiersURN: urn:nbn:se:liu:diva-28508DOI: 10.1109/DSD.2005.59Local ID: 13657ISBN: 0-7695-2433-8OAI: oai:DiVA.org:liu-28508DiVA: diva2:249318
8th Euromicro Conference on Digital System Design DSD2005