Validation of Embedded Systems using Formal Method aided Verification
2005 (English)In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, 196- p.Conference paper (Refereed)
Informal validation techniques, such as simulation, suffer from the fact that they only examine a small fraction of the state space. Formal techniques, on the other hand, suffer from state space explosion and are not practical to use for huge, complex systems. This paper proposes a validation approach, based on simulation, which addresses some of the above problems. Formal methods, in particular model checking, are used to aid the simulation process in certain situations in order to boost coverage. The invocation frequency of the model checker is dynamically controlled by estimating certain parameters, based on statistics collected previously during the same validation session, in order to minimise verification time and at the same time achieve reasonable coverage. The approach has been demonstrated feasible by numerous experimental results.
Place, publisher, year, edition, pages
Porto, Portugal: IEEE Computer Society Press , 2005. 196- p.
formal verification, validation approach, simulation, formal methods, model checker
IdentifiersURN: urn:nbn:se:liu:diva-28509DOI: 10.1109/DSD.2005.75Local ID: 13658ISBN: 0-7695-2433-8OAI: oai:DiVA.org:liu-28509DiVA: diva2:249319
8th Euromicro Conference on Digital System Design DSD2005