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High-Level Techniques for Built-In Self-Test Resources Optimization
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2005 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

Design modifications to improve testability usually introduce large area overhead and performance degradation. One way to reduce the negative impact associated with improved testability is to take testability as one of the constraints during high- level design phases so that systems are not only optimized for area and performance, but also from the testability point of view. This thesis deals with the problem of optimizing testing-hardware resources by taking into account testability constraints at high-levels of abstraction during the design process. Firstly, we have provided an approach to solve the problem of optimizing built-in selftest (BIST) resources at the behavioral and register-transfer levels under testability and testing time constraints. Testing problem identification and BIST enhancement during the optimization process are assisted by symbolic testability analysis. Further, concurrent test sessions are generated, while signature analysis registers sharing conflicts as well as controllability and observability constraints are considered. Secondly, we have introduced the problem of BIST resources insertion and optimization while taking wiring area into account. Testability improvement transformations have been defined and deployed in a hardware overhead minimization technique used during a BIST synthesis process. The technique is guided by the results of symbolic testability analysis and inserts a minimal amount of BIST resources into the design to make it fully testable. It takes into consideration both BIST components cost and wiring overhead. Two design space exploration approaches have been proposed: a simulated annealing based algorithm and a greedy heuristic. Experimental results show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. The greedy heuristic uses our behavioral and register-transfer levels BIST enhancement metrics to guide BIST synthesis in such a way that the number of testability improvement transformations performed on the design is reduced.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2005. , 115 p.
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1156
Keyword [en]
testing, system-on-chip, testability, built-in self-test, BIST, wiring-aware
National Category
Computer Science
URN: urn:nbn:se:liu:diva-28510Local ID: 13659ISBN: 91-85297-90-9OAI: diva2:249320
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2009-11-25Bibliographically approved

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Mohamed, Abdil
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ESLAB - Embedded Systems LaboratoryThe Institute of Technology
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