A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
2005 (English)In: Journal of Computer Science and Technology, ISSN 1000-9000, E-ISSN 1860-4749, Vol. 20, no 2, 216-223 p.Article in journal (Refereed) Published
This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.
Place, publisher, year, edition, pages
2005. Vol. 20, no 2, 216-223 p.
testing, build-in-self test, BIST, wiring-aware, optimization
IdentifiersURN: urn:nbn:se:liu:diva-29357DOI: 10.1007/s11390-005-0216-9Local ID: 14680OAI: oai:DiVA.org:liu-29357DiVA: diva2:250169