liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
SOC Test Scheduling with Test Set Sharing and Broadcasting
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2005 (English)In: IEEE Asian Test Symposium,2005, Kolkata, India: IEEE Computer Society Press , 2005, 162- p.Conference paper, Published paper (Refereed)
Abstract [en]

Due to the increasing test data volume needed to test core-based System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In contrast to approaches where a fixed test set for each core is assumed, we explore the possibility to use overlapping test patterns from the tests in the system. The overlapping tests serves as alternatives to the original dedicated test for the cores and, if selected, they are transported to the cores in a broadcasted manner so that several cores are tested concurrently. We have made use of a Constraint Logic Programming technique to select suitable tests for each core in the system and schedule the selected tests such that the test application time is minimized while designer-specified hardware constraints are satisfied. The experimental results indicate that we can on average reduce the test application time with 23%.

Place, publisher, year, edition, pages
Kolkata, India: IEEE Computer Society Press , 2005. 162- p.
Keyword [en]
testing, system-on-chip, test scheduling, overlapping test patterns, constraint logic programming
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-29359DOI: 10.1109/ATS.2005.100Local ID: 14682ISBN: 0-7695-2481-8 (print)OAI: oai:DiVA.org:liu-29359DiVA: diva2:250171
Conference
IEEE Asian Test Symposium,2005
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-08-16

Open Access in DiVA

No full text

Other links

Publisher's full texthttp://www.ida.liu.se/labs/eslab/publications/pap/db/andla_ats05.pdf

Authority records BETA

Larsson, AndersLarsson, ErikEles, Petru IonPeng, Zebo

Search in DiVA

By author/editor
Larsson, AndersLarsson, ErikEles, Petru IonPeng, Zebo
By organisation
The Institute of TechnologyESLAB - Embedded Systems Laboratory
Computer Science

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 131 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf