At present, focus of the SiC crystal growth development is on improving the crystalline quality without polytype inclusions, micropipes and the occurrence of extended defects. The purity of the grown material, as well as intentional doping must be well controlled and the processes understood. High-quality substrates will significantly improve device performance and yield. One of the aims of the licentiate thesis is further understanding of polytype inclusion formation as well as impurity control in SiC bulk crystals grown using PVT method also termed seeded sublimation method. We have identified a carbonization of the source as a major reason behind the polytype inclusion occurrence during the growth. The aim of this work was further understanding of sublimation growth process of 4H-SiC bulk crystals in vacuum, in absence of an inert gas. For comparison growth in argon atmosphere (at 5 mbar) was performed. The effect of the ambient on the impurity incorporation was studied for different growth temperatures. For better control of the process in vacuum, tantalum as a carbon getter was utilized.
The major focus of the thesis was put on further understanding of the PVT epitaxy with an emphasis on the high growth rate and the purity of grown layers.
High resistivity 4H-SiC samples grown by sublimation with high growth rate were studied. The measurements show resistivity values up to high 104 Ωcm. By correlation between the growth conditions and SIMS results, we apply a model in which it is proposed that an isolated carbon vacancy donor-like level is a possible candidate responsible for compensation of the shallow acceptors in p-type 4H-SiC. A relation between cathodoluminescence (CL) and DL TS data is taken into account to support the model.
To meet the requirements for high voltage blocking devices such as high voltage Schottky diodes and MOSFETs, 4H-SiC epitaxial layers have to exhibit low doping concentration in order to block reverse voltages up to few keV and at the same time have a low on-state resistance (Ron). High Ron leads to enhanced power consumption in the operation mode of the devices. In growth of thick layers for high voltage blocking devices, the conditions to achieve good on-state characteristics become more challenging due to the low doping and pronounced thicknesses needed, preferably in short growth periods. In case of high-speed epitaxy such as the sublimation, the need to apply higher growth temperature to yield the high growth rate, results in an increased concentration of background impurities in the layers as well as an influence on the intrinsic defects.
On-state resistance Ron estimated from current density-voltage characteristics of Schottky diodes on thick sublimation layers exhibits variations from tens of mΩ.cm2 to tens of Ω.cm2 for different doping levels. In order to understand the occurrence of high on-state resistance, Schottky barrier heights were first estimated for both forward and reverse bias with the application of thermionic emission theory and were in agreement with a literature reported values. Decrease in mobility with increasing temperature was observed and its dependencies of T-1.3 and T-2.0 for moderately doped and low doped samples, respectively, were estimated. From deep level measurements by Minority Carrier Transient Spectroscopy, an influence of shallow boron related levels and D-center on the on-state resistance was observed, being more pronounced in low doped samples. Similar tendency was observed in depth profiling of Ron. This suggests a major role of boron in a compensation mechanism.
Metal-Oxide-Semiconductor (MOS) capacitors were fabricated and characterized on 4H-SiC epilayers grown by PVT (sublimation) epitaxy and compared to the properties of similar structures on CVD grown layers. Detailed investigations of the PVT structures indicate a stable behaviour of the interface traps from roomtemperature up to 475 K. The amount of positive oxide charges Qo is 6.83x109 cm-2 at room temperature and decreases with temperature increase which suggests temperature stability of processed devices. The density of interface states Dit obtained by AC conductance method is lower in the case of PVT sample.
AI203 as an alternative gate dielectric was studied. The implementation of this high-k dielectric is required in the case of high electric fields at which the usage of SiO2 may result in the reliability problems. The electrical properties of AI2O3 as a gate dielectric in MOS structures based on n- and p-type 4H-SiC grown by sublimation method were investigated and compared to the properties of similar structures utilizing SiO2.
Linköping: Linköpings universitet , 2005. , 50 p.