Formal Verification of SystemC Designs Using a Petri-Net based Representation
2006 (English)In: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, 1228- p.Conference paper (Refereed)
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed temporal logic. The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments.
Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2006. 1228- p.
formal verification, SystemC, Petri-Net representation, temporal logic, model checking, transaction-level
IdentifiersURN: urn:nbn:se:liu:diva-31230DOI: 10.1109/DATE.2006.244076Local ID: 16983ISBN: 3-9810801-1-4OAI: oai:DiVA.org:liu-31230DiVA: diva2:252053
Design Automation and Test in Europe Conference DATE 2006