Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-offs for Distributed Embedded Systems
2006 (English)In: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, 706- p.Conference paper (Refereed)
In this paper we present an approach to the scheduling of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. If process recovery is performed such that the operation of other processes is not affected, we call it transparent recovery. Although transparent recovery has the advantages of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules, it will introduce delays that can violate the timing constraints of the application. We propose a novel algorithm for the synthesis of fault-tolerant schedules that can handle the transparency/performance trade-offs imposed by the designer, and makes use of the fault-occurrence information to reduce the overhead due to fault tolerance. We model the application as a conditional process graph, where the fault occurrence information is represented as conditional edges and the transparent recovery is captured using synchronization nodes.
Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2006. 706- p.
fault tolerance, multiple transient faults, scheduling, embedded systems, hard real-time, re-execution
IdentifiersURN: urn:nbn:se:liu:diva-31231DOI: 10.1109/DATE.2006.244067Local ID: 16984ISBN: 3-9810801-1-4OAI: oai:DiVA.org:liu-31231DiVA: diva2:252054
Design Automation and Test in Europe Conference DATE 2006