Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning
2006 (English)In: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, 291- p.Conference paper (Refereed)
This paper presents a test scheduling approach for system-on-chip production tests with peak-power constraints. An abort-on-first-fail test approach is assumed, whereby the test is terminated as soon as the first fault is detected. Defect probabilities of individual cores are used to guide the test scheduling and the peak-power constraint is considered in order to limit the test concurrency. Test set partitioning is used to divide a test set into several test sequences so that they can be tightly packed into the two-dimensional space of power and time. The partitioning of test sets is integrated into the test scheduling process. A heuristic has been developed to find an efficient test schedule which leads to reduced expected test time. Experimental results have shown the efficiency of the proposed test scheduling approach.
Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2006. 291- p.
testing, test scheduling, system-on-chip, peak-power constraints, abort-on-first-fail test approach
IdentifiersURN: urn:nbn:se:liu:diva-31236Local ID: 16989OAI: oai:DiVA.org:liu-31236DiVA: diva2:252059