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SoCBUS: switched network on chip for hard real time embedded systems
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2003 (English)In: Proceedings. International Parallel and Distributed Processing Symposium, 2003, 2003, 78- p.Conference paper, Published paper (Refereed)
Abstract [en]

With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth and simplify the interface verification. We have previously proposed a circuit switched two-dimensional mesh network known as SoCBUS that increases performance and lowers the cost of verification. In this paper, the SoCBUS is explained together with the working principles of the transaction handling. We also introduce the concept of packet connected circuit, PCC, where a packet is switched through the network locking the circuit as it goes. PCC is deadlock free and does not impose any unnecessary restrictions on the system while being simple and efficient in implementation. SoCBUS uses this PCC scheme to set up routes through the network. We introduce a possible application, a telephone to voice-over-IP gateway, and use this to show that the SoCBUS have very good properties in bandwidth, latency, and complexity when used in a hard real time system with scheduling of the traffic. The simulations analysis of the SoCBUS in the application show that a certain SoCBUS setup can handle 48000 channels of voice data including buffer swapping in a single chip. We also show that the SoCBUS is not suitable for general purpose computing platforms that exhibit random traffic patterns but that the SoCBUS show acceptable performance when the traffic is mainly local.

Place, publisher, year, edition, pages
2003. 78- p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-33271DOI: 10.1109/IPDPS.2003.1213180Local ID: 19271OAI: oai:DiVA.org:liu-33271DiVA: diva2:254094
Conference
International Parallel and Distributed Processing Symposium. Nice, France, 22-26 April, 2003.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
In thesis
1. An on-chip network architecture for hard real time systems
Open this publication in new window or tab >>An on-chip network architecture for hard real time systems
2003 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

With the ever increasing demands on processing power and communication on a single chip the industry is facing a huge obstacle in closing the gap between possible complexity and achieved complexity, the so called design gap. A possible path out of this is the increase (re-)use of intellectual property (IP) blocks from within the company or from other suppliers. We have identified the problem area in the on-chip communication between IP blocks where the time-division multiplex buses are quickly becoming saturated.

Another problem arising with the increased use of deep submicron manufacturing technologies is the relatively long delay of wires compared to the gates. This problem forces the synchronous part of a chip to either shrink or run at a slower speed. With the goals of keeping the clock rate and increasing the complexity the only feasible solution is to use smaller synchronous subsystems that communicate asynchronously. This approach is known as globally asynchronous but locally synchronous (GALS).

This thesis presents the work on a bus replacement for on-chip communication. The goal of this bus replacement is to achieve very high performance compared to the old solution while allowing for higher flexibility, GALS style implementation, and simpler verification of the system.

With this goal in mind we investigated the possible topologies for a switched on-chip network (OCN) and concluded that a 2-d mesh or torus is the most appropriate. To keep the latency low we decided on a pseudo-circuit switched network using the 2-d mesh. We have developed a novel approach for route setup in the circuit switched network called packet connected circuit (PCC) which allows very short latency both for routing and payload transfer while having a very low silicon cost.

A simulator for this network has been implemented together with behavioral models of the network components. Simulations have shown that the PCC concept is not very suitable for general purpose processing platforms but that it is very suitable for a hard real time system that uses some communication scheduling.

Place, publisher, year, edition, pages
Linköping: Inivserv, 2003. 37 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 996
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33279 (URN)19279 (Local ID)91-7373-577-9 (ISBN)19279 (Archive number)19279 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15

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Publisher's full texthttp://www.da.isy.liu.se/pubs/danwi/danwi-ipdps2003.pdf

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Wiklund, DanielLiu, Dake

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