SoCBUS: switched network on chip for hard real time embedded systems
2003 (English)In: Proceedings. International Parallel and Distributed Processing Symposium, 2003, 2003, 78- p.Conference paper (Refereed)
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth and simplify the interface verification. We have previously proposed a circuit switched two-dimensional mesh network known as SoCBUS that increases performance and lowers the cost of verification. In this paper, the SoCBUS is explained together with the working principles of the transaction handling. We also introduce the concept of packet connected circuit, PCC, where a packet is switched through the network locking the circuit as it goes. PCC is deadlock free and does not impose any unnecessary restrictions on the system while being simple and efficient in implementation. SoCBUS uses this PCC scheme to set up routes through the network. We introduce a possible application, a telephone to voice-over-IP gateway, and use this to show that the SoCBUS have very good properties in bandwidth, latency, and complexity when used in a hard real time system with scheduling of the traffic. The simulations analysis of the SoCBUS in the application show that a certain SoCBUS setup can handle 48000 channels of voice data including buffer swapping in a single chip. We also show that the SoCBUS is not suitable for general purpose computing platforms that exhibit random traffic patterns but that the SoCBUS show acceptable performance when the traffic is mainly local.
Place, publisher, year, edition, pages
2003. 78- p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-33271DOI: 10.1109/IPDPS.2003.1213180Local ID: 19271OAI: oai:DiVA.org:liu-33271DiVA: diva2:254094
International Parallel and Distributed Processing Symposium. Nice, France, 22-26 April, 2003.