Packet Classification and Termination in a Protocol Processor
2003 (English)Conference paper (Other academic)
This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.
Place, publisher, year, edition, pages
2003. 88- p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-33275Local ID: 19275OAI: oai:DiVA.org:liu-33275DiVA: diva2:254098
Ninth International Symposium on High Performance Computer Architecture. Anaheim, California, February 8-12, 2003.