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Packet Classification and Termination in a Protocol Processor
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2003 (English)Conference paper, Published paper (Other academic)
Abstract [en]

This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

Place, publisher, year, edition, pages
2003. 88- p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-33275Local ID: 19275OAI: oai:DiVA.org:liu-33275DiVA: diva2:254098
Conference
Ninth International Symposium on High Performance Computer Architecture. Anaheim, California, February 8-12, 2003.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
In thesis
1. A Programmable Network Interface Accelerator
Open this publication in new window or tab >>A Programmable Network Interface Accelerator
2003 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures.

In the emerging research area of programmable network interfaces, there exist many hardware platform proposals. Most of them aim for router applications but not so many for terminals. This thesis explores a number of different router design alternatives and architectural concepts. The concepts have been examined to see which apply also to terminal designs.

A novel terminal platform solution is proposed in this thesis. The platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, that operates in parallel, to accelerate the platform. The hardware blocks have been selected and specified to fulfill the requirements set by a number of common network protocols. To do this, the protocol processing procedure has been investigated and divided into processing tasks. The different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in other parts of the platform.

The dedicated datapath, simplified control, and minimal usage of data buffers makes the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled.

Place, publisher, year, edition, pages
Linköping: Uniserv, 2003. 63 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 998
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33282 (URN)19282 (Local ID)91-7373-580-9 (ISBN)19282 (Archive number)19282 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15

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http://www.da.isy.liu.se/pubs/ulfnor/ulfnor-hpca2003.pdf

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Nordqvist, UlfLiu, Dake

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Citation style
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Output format
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  • text
  • asciidoc
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