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An on-chip network architecture for hard real time systems
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2003 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

With the ever increasing demands on processing power and communication on a single chip the industry is facing a huge obstacle in closing the gap between possible complexity and achieved complexity, the so called design gap. A possible path out of this is the increase (re-)use of intellectual property (IP) blocks from within the company or from other suppliers. We have identified the problem area in the on-chip communication between IP blocks where the time-division multiplex buses are quickly becoming saturated.

Another problem arising with the increased use of deep submicron manufacturing technologies is the relatively long delay of wires compared to the gates. This problem forces the synchronous part of a chip to either shrink or run at a slower speed. With the goals of keeping the clock rate and increasing the complexity the only feasible solution is to use smaller synchronous subsystems that communicate asynchronously. This approach is known as globally asynchronous but locally synchronous (GALS).

This thesis presents the work on a bus replacement for on-chip communication. The goal of this bus replacement is to achieve very high performance compared to the old solution while allowing for higher flexibility, GALS style implementation, and simpler verification of the system.

With this goal in mind we investigated the possible topologies for a switched on-chip network (OCN) and concluded that a 2-d mesh or torus is the most appropriate. To keep the latency low we decided on a pseudo-circuit switched network using the 2-d mesh. We have developed a novel approach for route setup in the circuit switched network called packet connected circuit (PCC) which allows very short latency both for routing and payload transfer while having a very low silicon cost.

A simulator for this network has been implemented together with behavioral models of the network components. Simulations have shown that the PCC concept is not very suitable for general purpose processing platforms but that it is very suitable for a hard real time system that uses some communication scheduling.

Place, publisher, year, edition, pages
Linköping: Inivserv , 2003. , 37 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 996
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-33279Local ID: 19279ISBN: 91-7373-577-9 (print)OAI: oai:DiVA.org:liu-33279DiVA: diva2:254102
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
List of papers
1. Switched interconnect for system-on-a-chip design
Open this publication in new window or tab >>Switched interconnect for system-on-a-chip design
2000 (English)In: Proceedings of the IP2000 Europe Conference, 2000, 185-192 p.Conference paper, Published paper (Other academic)
Abstract [en]

With the increased use of IP cores in chip designs, an increasing amount of time is spent on design and verification of glue logic. To solve this problem together with the bottleneck problem of arbitration based buses, a novel approach in system-on-a-chip interconnect has been investigated. The approach is based on a switched interconnect structure, with small crossbar switches connected in a mesh for intercore communications with low latency in system-on-chip solutions. The interfaces between the interconnect network and the cores are handled by configurable wrappers that adapt the port parameters from core to network format. The core functionality of the interconnect network can be fully verified with a fairly low work effort even when configurable, so the main problem for cutting verification time is the quite complex wrappers. The concept is to make the wrappers highly configurable yet needing short verification time in an application by making a fairly complete verification of the wrappers for all configurations. How this can be achieved is under investigation. The approach described in this paper is mainly aimed for use in communication equipment where high bandwidth and low latency is essential.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100987 (URN)
Conference
IP2000 Europe Conference. Edinburgh, Scotland, 2000
Available from: 2013-11-15 Created: 2013-11-15 Last updated: 2013-11-15
2. Design of a system-on-chip switched network and its design support
Open this publication in new window or tab >>Design of a system-on-chip switched network and its design support
2002 (English)In: IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002, 1279-1283 p.Conference paper, Published paper (Refereed)
Abstract [en]

As the degree of integration increases, the on-chip communication is becoming a bottleneck. A solution to this problem is to use an on-chip switched interconnect network. Such a system-on-chip network was proposed in 2000 by the same authors. In this paper, we present the system-on-chip network in detail together with the design flow support. The choice of topology for the network, as well as some ways to use the network to overcome the future physical implementation issues of wire delay, and to gain performance, is also discussed. To aid the design choices of the network, a behavioral simulator has been created. The importance of the behavioral simulator is clearly shown from the design flow and the design and implementation of this simulator is discussed in detail.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33551 (URN)10.1109/ICCCAS.2002.1179016 (DOI)19576 (Local ID)0-7803-7547-5 (ISBN)19576 (Archive number)19576 (OAI)
Conference
International Conference on Communications, Circuits and Systems and West Sino Expositions (ICCCAS), Chengdu, China. 29 June - 1 July. 2002.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
3. SoCBUS: switched network on chip for hard real time embedded systems
Open this publication in new window or tab >>SoCBUS: switched network on chip for hard real time embedded systems
2003 (English)In: Proceedings. International Parallel and Distributed Processing Symposium, 2003, 2003, 78- p.Conference paper, Published paper (Refereed)
Abstract [en]

With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth and simplify the interface verification. We have previously proposed a circuit switched two-dimensional mesh network known as SoCBUS that increases performance and lowers the cost of verification. In this paper, the SoCBUS is explained together with the working principles of the transaction handling. We also introduce the concept of packet connected circuit, PCC, where a packet is switched through the network locking the circuit as it goes. PCC is deadlock free and does not impose any unnecessary restrictions on the system while being simple and efficient in implementation. SoCBUS uses this PCC scheme to set up routes through the network. We introduce a possible application, a telephone to voice-over-IP gateway, and use this to show that the SoCBUS have very good properties in bandwidth, latency, and complexity when used in a hard real time system with scheduling of the traffic. The simulations analysis of the SoCBUS in the application show that a certain SoCBUS setup can handle 48000 channels of voice data including buffer swapping in a single chip. We also show that the SoCBUS is not suitable for general purpose computing platforms that exhibit random traffic patterns but that the SoCBUS show acceptable performance when the traffic is mainly local.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33271 (URN)10.1109/IPDPS.2003.1213180 (DOI)19271 (Local ID)19271 (Archive number)19271 (OAI)
Conference
International Parallel and Distributed Processing Symposium. Nice, France, 22-26 April, 2003.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15

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