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A Programmable Network Interface Accelerator
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2003 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures.

In the emerging research area of programmable network interfaces, there exist many hardware platform proposals. Most of them aim for router applications but not so many for terminals. This thesis explores a number of different router design alternatives and architectural concepts. The concepts have been examined to see which apply also to terminal designs.

A novel terminal platform solution is proposed in this thesis. The platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, that operates in parallel, to accelerate the platform. The hardware blocks have been selected and specified to fulfill the requirements set by a number of common network protocols. To do this, the protocol processing procedure has been investigated and divided into processing tasks. The different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in other parts of the platform.

The dedicated datapath, simplified control, and minimal usage of data buffers makes the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled.

Place, publisher, year, edition, pages
Linköping: Uniserv , 2003. , 63 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 998
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-33282Local ID: 19282ISBN: 91-7373-580-9 (print)OAI: oai:DiVA.org:liu-33282DiVA: diva2:254105
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
List of papers
1. Configuration-based architecture for high speed and general-purpose protocol processing
Open this publication in new window or tab >>Configuration-based architecture for high speed and general-purpose protocol processing
1999 (English)In: 1999 IEEE Workshop on Signal Processing Systems, 1999. SiPS 99., 1999, 540-547 p.Conference paper, Published paper (Refereed)
Abstract [en]

A novel configuration based general-purpose protocol processor is proposed. It can perform much faster protocol processing compared to general-purpose processors. As it is configuration based, different protocols can be configured for different protocols and different applications. The configurability makes compatibility possible, it also processes protocols very fast on the fly. The proposed architecture can be used as a platform or an accelerator for network-based applications

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100980 (URN)10.1109/SIPS.1999.822360 (DOI)
Conference
SIPS 1999, 20-22 October. Taipei, Taiwan
Available from: 2013-11-15 Created: 2013-11-15 Last updated: 2013-11-15
2. CRC generation for protocol processing
Open this publication in new window or tab >>CRC generation for protocol processing
2000 (English)In: Proceedings of NORCHIP 2000, 2000, 288-293 p.Conference paper, Published paper (Refereed)
Abstract [en]

In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100981 (URN)
Conference
18th NORCHIP Conference, 6-7 November, 2000, Turku, Finland
Available from: 2013-11-15 Created: 2013-11-15 Last updated: 2014-12-19
3. Packet Classification and Termination in a Protocol Processor
Open this publication in new window or tab >>Packet Classification and Termination in a Protocol Processor
2003 (English)Conference paper, Published paper (Other academic)
Abstract [en]

This paper introduces a novel architecture for acceleration of control memory access in a protocol processor dedicated for packet reception in network terminals. The architecture ena'bles the protocol processor to perform high performance reassembly and also offtoads other parts of the control flow processing. The architecture includes packet classification engines and concepts used in modem high-speed routers. The protocol processor combined with a general purpose micro controller, fully offload up to layer 4 processing in multi gigabit networks when implemented in mature standard cell processes.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33275 (URN)19275 (Local ID)19275 (Archive number)19275 (OAI)
Conference
Ninth International Symposium on High Performance Computer Architecture. Anaheim, California, February 8-12, 2003.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15

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Nordqvist, Ulf

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Citation style
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