Instruction and hardware acceleration for MP-MLQ in G.723.1
2002 (English)In: IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02)., 2002, 235-239 p.Conference paper (Refereed)
This paper describes a significant improvement in complexity for the higher bit rate, 6.3 kbit/s, speech coding algorithm G.723.1. The solution is to reduce the number of multiplications of the most computing extensive part of the algorithm. This part stands for around 50% of the total complexity. This is done by identifying and excluding multiplication with zeros. G.723.1 is one of the proposed speech coders in the H.323 standard. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions. A hardware structure for an application specific instruction set processor (ASIP) is proposed to increase the performance.
Place, publisher, year, edition, pages
2002. 235-239 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-33543DOI: 10.1109/SIPS.2002.1049715Local ID: 19568ISBN: 0-7803-7587-4OAI: oai:DiVA.org:liu-33543DiVA: diva2:254366
IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02). San Diego, California, USA. October 16-18, 2002.