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Design of a system-on-chip switched network and its design support
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2002 (English)In: IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002, 1279-1283 p.Conference paper, Published paper (Refereed)
Abstract [en]

As the degree of integration increases, the on-chip communication is becoming a bottleneck. A solution to this problem is to use an on-chip switched interconnect network. Such a system-on-chip network was proposed in 2000 by the same authors. In this paper, we present the system-on-chip network in detail together with the design flow support. The choice of topology for the network, as well as some ways to use the network to overcome the future physical implementation issues of wire delay, and to gain performance, is also discussed. To aid the design choices of the network, a behavioral simulator has been created. The importance of the behavioral simulator is clearly shown from the design flow and the design and implementation of this simulator is discussed in detail.

Place, publisher, year, edition, pages
2002. 1279-1283 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-33551DOI: 10.1109/ICCCAS.2002.1179016Local ID: 19576ISBN: 0-7803-7547-5 (print)OAI: oai:DiVA.org:liu-33551DiVA: diva2:254374
Conference
International Conference on Communications, Circuits and Systems and West Sino Expositions (ICCCAS), Chengdu, China. 29 June - 1 July. 2002.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15
In thesis
1. An on-chip network architecture for hard real time systems
Open this publication in new window or tab >>An on-chip network architecture for hard real time systems
2003 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

With the ever increasing demands on processing power and communication on a single chip the industry is facing a huge obstacle in closing the gap between possible complexity and achieved complexity, the so called design gap. A possible path out of this is the increase (re-)use of intellectual property (IP) blocks from within the company or from other suppliers. We have identified the problem area in the on-chip communication between IP blocks where the time-division multiplex buses are quickly becoming saturated.

Another problem arising with the increased use of deep submicron manufacturing technologies is the relatively long delay of wires compared to the gates. This problem forces the synchronous part of a chip to either shrink or run at a slower speed. With the goals of keeping the clock rate and increasing the complexity the only feasible solution is to use smaller synchronous subsystems that communicate asynchronously. This approach is known as globally asynchronous but locally synchronous (GALS).

This thesis presents the work on a bus replacement for on-chip communication. The goal of this bus replacement is to achieve very high performance compared to the old solution while allowing for higher flexibility, GALS style implementation, and simpler verification of the system.

With this goal in mind we investigated the possible topologies for a switched on-chip network (OCN) and concluded that a 2-d mesh or torus is the most appropriate. To keep the latency low we decided on a pseudo-circuit switched network using the 2-d mesh. We have developed a novel approach for route setup in the circuit switched network called packet connected circuit (PCC) which allows very short latency both for routing and payload transfer while having a very low silicon cost.

A simulator for this network has been implemented together with behavioral models of the network components. Simulations have shown that the PCC concept is not very suitable for general purpose processing platforms but that it is very suitable for a hard real time system that uses some communication scheduling.

Place, publisher, year, edition, pages
Linköping: Inivserv, 2003. 37 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 996
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33279 (URN)19279 (Local ID)91-7373-577-9 (ISBN)19279 (Archive number)19279 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15

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Publisher's full texthttp://www.da.isy.liu.se/pubs/danwi/danwi-icccas2002.pdf

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Wiklund, DanielLiu, Dake

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