Design of a system-on-chip switched network and its design support
2002 (English)In: IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002, 1279-1283 p.Conference paper (Refereed)
As the degree of integration increases, the on-chip communication is becoming a bottleneck. A solution to this problem is to use an on-chip switched interconnect network. Such a system-on-chip network was proposed in 2000 by the same authors. In this paper, we present the system-on-chip network in detail together with the design flow support. The choice of topology for the network, as well as some ways to use the network to overcome the future physical implementation issues of wire delay, and to gain performance, is also discussed. To aid the design choices of the network, a behavioral simulator has been created. The importance of the behavioral simulator is clearly shown from the design flow and the design and implementation of this simulator is discussed in detail.
Place, publisher, year, edition, pages
2002. 1279-1283 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-33551DOI: 10.1109/ICCCAS.2002.1179016Local ID: 19576ISBN: 0-7803-7547-5OAI: oai:DiVA.org:liu-33551DiVA: diva2:254374
International Conference on Communications, Circuits and Systems and West Sino Expositions (ICCCAS), Chengdu, China. 29 June - 1 July. 2002.