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Specification of a configurable general-purpose protocol processor
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
2002 (English)In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, no 3, 198-202 p.Article in journal (Refereed) Published
Abstract [en]

A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. The paper defines a functional coverage, analyses the control requirements, and specifies functional pages and a controller unit. The general-purpose protocol processor is for network terminals, and therefore routing is not completely supported. However, it should be possible to use it as part of a router. with some minor modifications. The general-purpose protocol processor is partitioned into two parts: a configurable stand-alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program; instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions

Place, publisher, year, edition, pages
2002. Vol. 149, no 3, 198-202 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-33567DOI: 10.1049/ip-cds:20020443Local ID: 19599OAI: oai:DiVA.org:liu-33567DiVA: diva2:254390
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2017-12-13
In thesis
1. Hardware Architecture for Protocol Processing
Open this publication in new window or tab >>Hardware Architecture for Protocol Processing
2001 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Protocol processing is increasingly important. Through the years the hardware architectures for network equipment have evolved constantly. It is important to make a difference between terminals and routers and the different processing tasks they encounter. It is also important to analyze in detail the functional coverage of a hardware architecture. The maximal supported line speed is also interesting and especially which functionality can be kept at this line speed.

There are some types of hardware architectures that have gained much anention in research and from industry. Among these application specific instruction set computers, RISC with optimized instruction sets and reconfigurable hardware architectures are most often used. Very many network processors have been presented that aim for routers. So far not many protocol processors for terminals have been suggested. In terminals the requirements are different, for example low power consumption is very important for battery powered terminals.

I and my colleagues have proposed a novel way to build a protocol processor for a terminal. The main concept is to use an array of reconfigurable functional pages, which are connected in a deep pipeline. This deep pipeline serial processor is supported by a micro controller for exception handling and configuration tasks. The most performance-critical functional page in an Ethemet TCP/lP environment is the cyclic redundancy check. We allocated and scheduled the cyclic redundancy check in parallel with other functions. After having investigated different solutions we found that our functional page for cyclic redundancy check can manage 10 Gb/s, if a 0.15 micron manufacturing process is used in combination with optimized RTL code and synthesis.

Our architecture allows extensive parallel operation. The functionality is partitioned into the autonomous functional pages, which work in parallel. This reduces control overhead and simplifies the verification process. Low control overhead and extensively parallel computations admit low-power operation. The designed processor handles reception processing on a single packet or frame. It works in parallel with the host processor and significantly reduces the workload on the host processor. The designed processor always operates at line speed and supports up to 10 Gb/s.

Place, publisher, year, edition, pages
Linköping: Uniserv, 2001. 38 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 911
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33604 (URN)19638 (Local ID)91-7373-209-5 (ISBN)19638 (Archive number)19638 (OAI)
Presentation
2001-12-14, Sal Algoritmen, Linköpings universitet, Linköping, 13:15 (Swedish)
Opponent
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-07

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Henriksson, TomasNordqvist, UlfLiu, Dake

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