Hardware Architecture for Protocol Processing
2001 (English)Licentiate thesis, comprehensive summary (Other academic)
Protocol processing is increasingly important. Through the years the hardware architectures for network equipment have evolved constantly. It is important to make a difference between terminals and routers and the different processing tasks they encounter. It is also important to analyze in detail the functional coverage of a hardware architecture. The maximal supported line speed is also interesting and especially which functionality can be kept at this line speed.
There are some types of hardware architectures that have gained much anention in research and from industry. Among these application specific instruction set computers, RISC with optimized instruction sets and reconfigurable hardware architectures are most often used. Very many network processors have been presented that aim for routers. So far not many protocol processors for terminals have been suggested. In terminals the requirements are different, for example low power consumption is very important for battery powered terminals.
I and my colleagues have proposed a novel way to build a protocol processor for a terminal. The main concept is to use an array of reconfigurable functional pages, which are connected in a deep pipeline. This deep pipeline serial processor is supported by a micro controller for exception handling and configuration tasks. The most performance-critical functional page in an Ethemet TCP/lP environment is the cyclic redundancy check. We allocated and scheduled the cyclic redundancy check in parallel with other functions. After having investigated different solutions we found that our functional page for cyclic redundancy check can manage 10 Gb/s, if a 0.15 micron manufacturing process is used in combination with optimized RTL code and synthesis.
Our architecture allows extensive parallel operation. The functionality is partitioned into the autonomous functional pages, which work in parallel. This reduces control overhead and simplifies the verification process. Low control overhead and extensively parallel computations admit low-power operation. The designed processor handles reception processing on a single packet or frame. It works in parallel with the host processor and significantly reduces the workload on the host processor. The designed processor always operates at line speed and supports up to 10 Gb/s.
Place, publisher, year, edition, pages
Linköping: Uniserv , 2001. , 38 p.
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 911
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-33604Local ID: 19638ISBN: 91-7373-209-5OAI: oai:DiVA.org:liu-33604DiVA: diva2:254427
2001-12-14, Sal Algoritmen, Linköpings universitet, Linköping, 13:15 (Swedish)
Jantsch, Axel, Associate Professor
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