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Hardware Architecture for Protocol Processing
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2001 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Protocol processing is increasingly important. Through the years the hardware architectures for network equipment have evolved constantly. It is important to make a difference between terminals and routers and the different processing tasks they encounter. It is also important to analyze in detail the functional coverage of a hardware architecture. The maximal supported line speed is also interesting and especially which functionality can be kept at this line speed.

There are some types of hardware architectures that have gained much anention in research and from industry. Among these application specific instruction set computers, RISC with optimized instruction sets and reconfigurable hardware architectures are most often used. Very many network processors have been presented that aim for routers. So far not many protocol processors for terminals have been suggested. In terminals the requirements are different, for example low power consumption is very important for battery powered terminals.

I and my colleagues have proposed a novel way to build a protocol processor for a terminal. The main concept is to use an array of reconfigurable functional pages, which are connected in a deep pipeline. This deep pipeline serial processor is supported by a micro controller for exception handling and configuration tasks. The most performance-critical functional page in an Ethemet TCP/lP environment is the cyclic redundancy check. We allocated and scheduled the cyclic redundancy check in parallel with other functions. After having investigated different solutions we found that our functional page for cyclic redundancy check can manage 10 Gb/s, if a 0.15 micron manufacturing process is used in combination with optimized RTL code and synthesis.

Our architecture allows extensive parallel operation. The functionality is partitioned into the autonomous functional pages, which work in parallel. This reduces control overhead and simplifies the verification process. Low control overhead and extensively parallel computations admit low-power operation. The designed processor handles reception processing on a single packet or frame. It works in parallel with the host processor and significantly reduces the workload on the host processor. The designed processor always operates at line speed and supports up to 10 Gb/s.

Place, publisher, year, edition, pages
Linköping: Uniserv , 2001. , 38 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 911
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-33604Local ID: 19638ISBN: 91-7373-209-5 (print)OAI: oai:DiVA.org:liu-33604DiVA: diva2:254427
Presentation
2001-12-14, Sal Algoritmen, Linköpings universitet, Linköping, 13:15 (Swedish)
Opponent
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-07
List of papers
1. Configurable Port Processor Increases Flexibility in the Protocol Processing Area
Open this publication in new window or tab >>Configurable Port Processor Increases Flexibility in the Protocol Processing Area
2000 (English)In: Proceedings of COOLChips III An International Symposium on Low-Power and High-Speed Chips, 2000, 275- p.Conference paper, Published paper (Other academic)
Abstract [en]

The limitation in networking is no longer only the physical transmission media but also the end equipment, which has to process the protocol control fields. In most end terminals this processing has been performed by the main processor, but different types of co-processor have lately appeared to relieve it from this task. These co-processors have high power consumption since they are based on a RISC core. Instead ASIC:s can be used, but they lack flexibility and are specific for only one single protocol. It is clear that a new approach is needed.

(...)

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100437 (URN)
Conference
COOLChips III An International Symposium on Low-Power and High-Speed Chips. Kikai-Shinko-Kaikan, Tokyo, Japan. April 24-25. 2000
Available from: 2013-11-07 Created: 2013-11-07 Last updated: 2013-11-07
2. Specification of a configurable general-purpose protocol processor
Open this publication in new window or tab >>Specification of a configurable general-purpose protocol processor
2000 (English)In: Proceedings of Second International Symposium on Communication Systems, Networks and Digital Signal Processing, 2000, 284-289 p.Conference paper, Published paper (Other academic)
Abstract [en]

A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. This paper defines a functional coverage, analyses the control requirements, specifies functional pages and a controller unit. The general-purpose protocol processor is aimed for network terminals, therefore routing is not completely supported. However it should be possible to use it as part of a router with some minor modifications. The general-purpose protocol processor is partitioned into two parts, a configurable stand alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program, instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100439 (URN)
Conference
Second International Symposium on Communication Systems, Networks and Digital Signal Processing. Bournemouth, UK. July 19-20. 2000
Available from: 2013-11-07 Created: 2013-11-07 Last updated: 2013-11-07
3. VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
Open this publication in new window or tab >>VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
Show others...
2001 (English)In: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, 1215-1218 p.Conference paper, Published paper (Refereed)
Abstract [en]

For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33606 (URN)10.1109/ICECS.2001.957433 (DOI)19640 (Local ID)19640 (Archive number)19640 (OAI)
Conference
The 8th IEEE Internationa Conference on Electronics, Circuits and Systems, Malta, September 2-5, 2001
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-07
4. Specification of a configurable general-purpose protocol processor
Open this publication in new window or tab >>Specification of a configurable general-purpose protocol processor
2002 (English)In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, no 3, 198-202 p.Article in journal (Refereed) Published
Abstract [en]

A general-purpose protocol processor is specified with a dedicated architecture for protocol processing. The paper defines a functional coverage, analyses the control requirements, and specifies functional pages and a controller unit. The general-purpose protocol processor is for network terminals, and therefore routing is not completely supported. However, it should be possible to use it as part of a router. with some minor modifications. The general-purpose protocol processor is partitioned into two parts: a configurable stand-alone part and a program based microcontroller. The configurable part performs the protocol processing without any running program. The processor does not execute any cycle based program; instead execution is controlled by configuration vectors and control vectors. The microcontroller assists with the interface to the host processor and handles the configuration. It is concluded that by partitioning the control into three levels, the architecture is flexible and verification is simplified. The proposed architecture also has higher performance and lower power dissipation than other solutions

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33567 (URN)10.1049/ip-cds:20020443 (DOI)19599 (Local ID)19599 (Archive number)19599 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2017-12-13

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