Instruction and Hardware Acceleration in G.723.1 (6.3/5.3) and G.729
2001 (English)In: Proceedings of the 1st IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2001, 34-39 p.Conference paper (Refereed)
This paper makes accelerations on instruction level based on the three speech coding algorithms G.723.1, 6.3 kbit/s and 5.3 kbit/s and G.729 8 kbit/s with hardware implementation. All these three algorithms are proposed by the H.323 standard together with G.711 64 kbit/s and G.728 16 kbit/s. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions [I], . Three hardware structures are proposed to increase the performance.
Place, publisher, year, edition, pages
2001. 34-39 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-33605Local ID: 19639OAI: oai:DiVA.org:liu-33605DiVA: diva2:254428
The 1st IEEE International Symposium on Signal Processing and Information Technology, December 28-30, 2001, Cairo, Egypt