VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
2001 (English)In: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, 1215-1218 p.Conference paper (Refereed)
For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology
Place, publisher, year, edition, pages
2001. 1215-1218 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-33606DOI: 10.1109/ICECS.2001.957433Local ID: 19640OAI: oai:DiVA.org:liu-33606DiVA: diva2:254429
The 8th IEEE Internationa Conference on Electronics, Circuits and Systems, Malta, September 2-5, 2001