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Low-Power Low-Jitter Clock Generation and Distribution
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded.

The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz.

In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz.

Abstract [sv]

Mikroprocessorer till dagens datorer innehåller hundratals miljoner transistorersom utför åtskilliga miljarder komplexa databeräkningar per sekund. I stort settalla operationer i dagens mikroprocessorer ordnas genom att synkronisera demmed en eller flera klocksignaler. Dessa signaler behöver ofta distribueras överhela chippet och driva alla synkroniseringskretsar med klockfrekvenser pååtskilliga miljarder svängningar per sekund. Detta utgör en stor utmaning förkretsdesigners på grund av att klocksignalerna behöver ha en extremt högtidsnoggranhet, vilket blir svårare och svårare att uppnå då chippen blir större.Idealt ska samma klocksignal nå alla synkroniseringskretsar exakt samtidigt föratt uppnå optimal prestanda, avvikelser ifrån denna ideala funktionalitet innebärlägre prestanda. Ytterliggare utmaningar inom klockning av digitala chip, är atten betydande andel av processorns totala effekt förbrukas i klockdistributionen.Därför krävs nya innovativa kretslösningar för att lösa problemen med bådeonoggrannheten och den växande effektförbrukningen i klockdistributionen.

att lösa de problem som finns i dagens konventionella kretslösningar förklocksignaler på chip. I den första delen av denna avhandling presenterasforskningsresultat på oscillatorer vilka utgör mycket viktiga komponenter igeneringen av klocksignalerna på chippen. Teoretiska studier avfaslåsningsfenomen i integrerade klockoscillatorer har presenterats. Studiernahar visat att det finns stor potential för reducering av tidsonoggrannhet iklocksignalerna med hjälp av faslåsning till en annan signal. I avhandlingensförsta del presenteras även en diskussion om klockgeneratorer baserade påfördröjningslåsta element. Dessa fördröjningslåsta elementen, kända som DLLkretsar, har egenskapen att de kan fördröja en klocksignal med en bestämdfördröjning, vilket möjliggör skapandet av multipla klockfaser. En nykretsteknik har introducerats för klockgenerering av multipla klockfaser vilken reducerar effektförbrukningen och onoggranheten i DLL-baseradeklockgeneratorer. I denna teknik används en övervakningskrets vilken ser till attalla delar i klockgeneratorn utnyttjas effektivt och att oanvända kretsarinaktiveras. Baserat på experimentalla mätresultat från tillverkade testkretsar ikisel har en effektbesparing på mer än 10% uppvisats vid klockfrekvenser påupp till 2.5 GHz tillsammans med en betydande ökning av klocknoggranheten.

I avhandlingens andra del diskuteras en klockdistributionsteknik som baseraspå resonans, vilken har visat sig vara ett lovande alternativ till konventionllabufferdrivna klockningstekniker när det gäller minskande effektförbrukning.Principen bakom tekniken är att återanvända den energi som utnyttjas till attladda upp klocklasten. Teoretiska resonemang har visat att storaenergibesparingar är möjliga, och praktiska mätningar på tillverkadeexperimentchip har visat att effektförbrukingen kan mer än halveras. Ettproblem med den föreslagna klockningstekniken är att data som används iberäkningarna kretsen direkt påverkar klocklasten, vilket även påverkarnoggranheten på klocksignalen. För att komma till rätta med detta problemetpresenteras en teknik, baserad på forskning inom ovan nämndafaslåsningsfenomen, som kan minska onoggrannheten på klocksignalen medöver 50%. Både effektbesparingen och förbättringen av tidsnoggranheten harverifierats med hjälp av mätningar på tillverkade chip vid frekvenser upp mot1.8 GHz.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2008. , 161 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1208
Keyword [en]
Low-power, resonant clock distribution, injection locking, DLL-based clock generation, jitter suppression, CMOS
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-14896ISBN: 978-91-7393-817-4 (print)OAI: oai:DiVA.org:liu-14896DiVA: diva2:25513
Public defence
2008-10-10, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2017-07-07Bibliographically approved
List of papers
1. A Study of Injection Locking in Ring Oscillators
Open this publication in new window or tab >>A Study of Injection Locking in Ring Oscillators
2005 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, 5465-5468 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

Keyword
injection locking, ring oscillators, phase noise, jitter
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14043 (URN)10.1109/ISCAS.2005.1465873 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2009-05-27Bibliographically approved
2. A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
Open this publication in new window or tab >>A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
2006 (English)In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, 5143-5146 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

Keyword
quadrature VCO, tuning range, coupled ring oscillators, CMOS
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14046 (URN)10.1109/ISCAS.2006.1693790 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2011-02-15Bibliographically approved
3. First-Harmonic Injection-Locked Ring Oscillators
Open this publication in new window or tab >>First-Harmonic Injection-Locked Ring Oscillators
2006 (English)In: Proceedings of the IEEE Custom Integrated Circuit Conference (CICC), 10-13 September, San José, CA, USA, 2006, 733-736 p.Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed

Keyword
CMOS integrated circuits, frequency multipliers, harmonic oscillators (circuits), injection locked oscillators, logic circuits
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14893 (URN)10.1109/CICC.2006.320927 (DOI)
Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2011-02-14
4. A Study of First-Harmonic Injection Locking for On-chip Applications
Open this publication in new window or tab >>A Study of First-Harmonic Injection Locking for On-chip Applications
(English)Manuscript (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14894 (URN)
Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2010-01-14
5. 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, 464-467 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

Keyword
CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2010-01-14Bibliographically approved
6. Jitter Characteristic in Charge Recovery Resonant Clock Distribution
Open this publication in new window or tab >>Jitter Characteristic in Charge Recovery Resonant Clock Distribution
2007 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 7, 1618-1625 p.Article in journal (Refereed) Published
Abstract [en]

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

Keyword
CMOS digital integrated circuits, clocks, jitter, resonators
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14898 (URN)10.1109/JSSC.2007.896691 (DOI)
Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2017-12-13
7. Low-Power Bufferless Resonant Clock Distribution Networks
Open this publication in new window or tab >>Low-Power Bufferless Resonant Clock Distribution Networks
2007 (English)In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Montreal: ReSMiQ , 2007, 960-963 p.Conference paper, Published paper (Refereed)
Abstract [en]

The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.

Place, publisher, year, edition, pages
Montreal: ReSMiQ, 2007
Keyword
CMOS integrated circuits, VLSI, clocks, timing jitter
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14900 (URN)10.1109/MWSCAS.2007.4488725 (DOI)
Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2009-05-08

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