Jitter Characteristic in Charge Recovery Resonant Clock Distribution
2007 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 42, no 7, 1618-1625 p.Article in journal (Refereed) Published
This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.
Place, publisher, year, edition, pages
2007. Vol. 42, no 7, 1618-1625 p.
CMOS digital integrated circuits, clocks, jitter, resonators
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-14898DOI: 10.1109/JSSC.2007.896691OAI: oai:DiVA.org:liu-14898DiVA: diva2:25519