Low-Power Bufferless Resonant Clock Distribution Networks
2007 (English)In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Montreal: ReSMiQ , 2007, 960-963 p.Conference paper (Refereed)
The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.
Place, publisher, year, edition, pages
Montreal: ReSMiQ , 2007. 960-963 p.
CMOS integrated circuits, VLSI, clocks, timing jitter
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-14900DOI: 10.1109/MWSCAS.2007.4488725OAI: oai:DiVA.org:liu-14900DiVA: diva2:25522