Design and evaluation of a comparator in CMOS SOI
2005 (English)In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper (Other academic)
The purpose of this work is to find good design techniques for the analog/mixed-signal parts of a system-onchip in SOI. A comparator has therefore been designed and manufactured in a 0.13 um partially depleted SOI CMOS technology. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz, or above. An introduction to the silicon-on-insulator (SOI) technology is also given and some of the major advantages and disadvantages of using SOI are presented.
Place, publisher, year, edition, pages
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-34483Local ID: 21523OAI: oai:DiVA.org:liu-34483DiVA: diva2:255331