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A 1.8V 10-bit 80MS/s Low Power Track-and-Hold Circuit in a 0.18µm CMOS Process
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
2003 (English)In: IEEE International Symposium on Circuits and Systems, ISCAS,2003, 2003Conference paper, Published paper (Other academic)
Abstract [en]

A 10-bit low power track-and-hold (T&H) circuit aimed for the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T&H is sampling at 80MS/s, has a 30MHz analog bandwidth and was designed in a 0.18um CMOS process with a supply voltage of 1.8 Volt. A switched capacitor topology applying correlated double sampling is used for the T&H circuit and the amplifier is a folded cascode OTA with gain boosting. This paper describes the design of the complete T&H, including the derivation of the specifications as well as a straightforward approach for designing the transmission gate switches.

Place, publisher, year, edition, pages
2003.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34486Local ID: 21527OAI: oai:DiVA.org:liu-34486DiVA: diva2:255334
Available from: 2009-10-10 Created: 2009-10-10

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http://www.es.isy.liu.se/publications/papers_and_reports/2003/paper_ISCAS2003_FINAL.pdf

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Säll, Erik

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  • apa
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