Synchronous Latency-Insensitive Design for Multiple Clock Domain
2005 (English)In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), IEEE Explore , 2005, 83-86 p.Conference paper (Refereed)
Modern system-on-chip designs often require multiple clock frequencies. On the other hand, global interconnects suffer large delays. This paper proposes a method that manages these two problems within the framework of conventional synchronous design flow. The design is partitioned into isochronous blocks already at behavioral level, where each block is synchronous using a local clock. The local clock frequencies are assumed related by rational numbers. Communication between blocks is managed with FIFOs at each receiver, which manage different clock frequencies and hide unknown delays or clock skews. This method guarantees clock true implementation of a clock true behavioral description utilizing a predefined block-to-block latency.
Place, publisher, year, edition, pages
IEEE Explore , 2005. 83-86 p.
clocks, integrated circuit design, integrated circuit interconnections, system-on-chip
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-14906DOI: 10.1109/SOCC.2005.1554462OAI: oai:DiVA.org:liu-14906DiVA: diva2:25536