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DESIGN OF A SCALABLE DSP PROCESSOR
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
2005 (English)In: RVK,2005, Proceedings: RVK , 2005Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes the design of an on-going implementation of a fixed-point DSP processor with variable word length. Based on the top-down design approach described in [1], we discuss the approach based on a sequence of models and stepwise refinements. The pros and cons of selecting different models are investigated as they are compared with each other. For the purpose of validation, a flexible framework has been developed. It allows regression testing and dynamic changing of the test data set and model to be tested. Using the tools, the output is then automatically compared with the expected result as provided by the golden model. The project status today is a synthezisable VHDL model validated using backannotation and VITAL libraries

Place, publisher, year, edition, pages
Proceedings: RVK , 2005.
Keyword [en]
dsp, VHDL, top-down
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34535Local ID: 21722OAI: oai:DiVA.org:liu-34535DiVA: diva2:255383
Available from: 2009-10-10 Created: 2009-10-10

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Johansson, ThomasThalin, PatrikLindblad, UlrikWanhammar, Lars

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