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Offset Loopback Test For IC RF Transceivers
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2006 (English)In: Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz , 2006, 583-586 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we develop an offset loopback test setup for integrated RF transceivers (TRx's). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRx's). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade

Place, publisher, year, edition, pages
Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz , 2006. 583-586 p.
Keyword [en]
RF test, DfT, radio transceivers, RF-CMOS design
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34570DOI: 10.1109/MIXDES.2006.1706647Local ID: 21895ISBN: 83-922632-2-7 (print)OAI: oai:DiVA.org:liu-34570DiVA: diva2:255418
Conference
IEEE Mixed Design of Integrated Circuits and Systems Conference (MIXDES). Gdynia, Poland. 22-24 June 2006.
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-11-22
In thesis
1. Flexible wireless receivers: on-chip testing techniques and design for test
Open this publication in new window or tab >>Flexible wireless receivers: on-chip testing techniques and design for test
2008 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to commercial essential. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media from single wireless terminal. In RF perspective, these standards differ in frequency band, sensiti vity, data rate, bandwidth, and modulation type. Therefore, a reconfigurable multistandard radio receiver covering most of the cellular, WLAN and short range standards (800MHz-6GHz band) is required. To keep the cost low, high level of integration becomes a necessity for multistandard radio.

Recently, due to aggressive CMOS scaling ƒT of the transistors has reached the value of hundred of GHz. Moreover, CMOS technology is best suited for monolithic integration, so it seems to be the future choice for the realization of such a reconfigurable multistandard receiver. In this thesis, a multiband sampling radio receiver front-end with test circuitry (Off) implemented in 0.13μm CMOS is presented, which is one step ahead in this direction.

In modem radio transceivers, the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF transceivers. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow even before packaging. In this thesis, two onchip testing techniques to reduce the test time and cost are presented. The first addresses an offset loopback test for integrated RF transceivers which are not suitable for direct loopback. The other is a new technique for symbol error rate test (SER) that is better in sensitivity and test time compared to traditional SER test.

The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (Off) and circuit under test (CUT) are affected by these variations. In order to compensate the impact of large process variations on Off circuitry, a new calibration scheme using DC on-chip measurements supported by Artificial Neural Networks (ANN) as a statistical regression method is presented.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2008. 96 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1378
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-43570 (URN)74243 (Local ID)978-91-7393-816-7 (ISBN)74243 (Archive number)74243 (OAI)
Presentation
2008-09-09, Glashuset, Linköpings Universitet, Linköping, 00:00 (Swedish)
Opponent
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-11-22

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Dabrowski, JerzyRashad, Ramzan

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