Implementation of low-complexity FIR filters using serial arithmetic
2005 (English)In: IEEE Int. Symp. Circuits Syst.,2005, Piscataway, NJ: IEEE , 2005, II/1449- p.Conference paper (Refereed)
The effects of digit-size on FIR filters implemented using multiplier block techniques are studied. Two different multiplier block algorithms are considered, one that minimizes the number of adders without considering the number of shifts and one that minimizes the number of shifts while keeping the number of adders low. Results on area, sample rate, and power consumption are presented, focusing on the arithmetic parts of the FIR filter.
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2005. II/1449- p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34589Local ID: 22192OAI: oai:DiVA.org:liu-34589DiVA: diva2:255437