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A Low Power Decimation Filter Architecture for High-Speed Single-Bit Sigma-Delta Modulation
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.ORCID iD: 0000-0003-3470-3911
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
2005 (English)In: IEEE International Symposium on Circuits and Systems,2005, Piscataway, NJ: IEEE , 2005, 1453- p.Conference paper, Published paper (Refereed)
Abstract [en]

In this work a novel architecture suitable for high-speed FIR decimation filters for single-bit sigma-delta modulation is proposed. By using efficient data and coefficient representation the total number of partial products is reduced leading to low power consumption. The work is focused on filters designed based on cascaded comb filters, although the approach is applicable to any FIR filter.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2005. 1453- p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34590Local ID: 22193OAI: oai:DiVA.org:liu-34590DiVA: diva2:255438
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11

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http://ieeexplore.ieee.org/iel5/9898/31469/01464872.pdf

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Gustafsson, OscarOhlsson, Henrik

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CiteExportLink to record
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  • apa
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