A Low Power Decimation Filter Architecture for High-Speed Single-Bit Sigma-Delta Modulation
2005 (English)In: IEEE International Symposium on Circuits and Systems,2005, Piscataway, NJ: IEEE , 2005, 1453- p.Conference paper (Refereed)
In this work a novel architecture suitable for high-speed FIR decimation filters for single-bit sigma-delta modulation is proposed. By using efficient data and coefficient representation the total number of partial products is reduced leading to low power consumption. The work is focused on filters designed based on cascaded comb filters, although the approach is applicable to any FIR filter.
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2005. 1453- p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34590Local ID: 22193OAI: oai:DiVA.org:liu-34590DiVA: diva2:255438