Trade-offs in low power multiplier blocks using serial arithmetic
2005 (English)In: National Conf. Radio Science RVK,2005, Linköping: RVK , 2005, 271-274 p.Conference paper (Refereed)
In this paper trade-offs in multiplier blocks are studied.
Three different algorithms for realization of multiplier
blocks are compared in terms of complexity, logic depth,
and power consumption. A new algorithm that reduces the
number of shifts while the number of adders is on average
the same is presented. Hence, the total complexity is reduced for multiplier blocks implemented using serial
arithmetic, where shift operations has a cost. The design of
low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main
factor that need to be considered is logic depth.
Place, publisher, year, edition, pages
Linköping: RVK , 2005. 271-274 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34595Local ID: 22198OAI: oai:DiVA.org:liu-34595DiVA: diva2:255443