Simplified Design of Constant Coefficient Multipliers
2006 (English)In: Circuits, systems, and signal processing, ISSN 0278-081X, Vol. 25, no 2, 225-251 p.Article in journal (Refereed) Published
In many digital signal processing algorithms, e.g., linear transforms and digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work two approaches to realize constant coefficient multiplication with few adders and subtracters are presented. The first yields optimal results, i.e., a minimum number of adders and subtracters, but requires an exhaustive search. Compared with previous optimal approaches, redundancies in the exhaustive search cause the search time to be drastically decreased. The second is a heuristic approach based on signed-digit representation and subexpression sharing. The results for the heuristic are worse in only approximately 1% of all coefficients up to 19 bits. However, the optimal approach results in several different optimal realizations, from which it is possible to pick the best one based on other criteria. Relations between the number of adders, possible coefficients, and number of cascaded adders are presented, as well as exact equations for the number of required full and half adder cells. The results show that the number of adders and subtracters decreases on average 25% for 19-bit coefficients compared with the canonic signed-digit representation.
Place, publisher, year, edition, pages
2006. Vol. 25, no 2, 225-251 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34596DOI: 10.1007/s00034-005-2505-5Local ID: 22199OAI: oai:DiVA.org:liu-34596DiVA: diva2:255444