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Bit-level pipelinable general and fixed coefficient digit-serial/parallel multipliers based on shift-accumulation
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.ORCID iD: 0000-0003-3470-3911
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
2002 (English)In: International Conference on Electronics, Circuits, and Systems,2002, Piscataway, NJ: IEEE , 2002, 493- p.Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we introduce a novel approach to digit-serial/parallel multiplication. This general class of multipliers is based on shift-accumulation which also makes the approach suitable for implementation of shift-accumulators in distributed arithmetic. As a variable in the design process, the maximal number of cascaded full-adders can be selected. Thus, it is possible to, as a special case, obtain a bit-level pipelined multiplier. Both general and fixed coefficient multiplication is considered. The hardware complexity is low compared with other approaches.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2002. 493- p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34599DOI: 10.1109/ICECS.2002.1046205Local ID: 22202OAI: oai:DiVA.org:liu-34599DiVA: diva2:255447
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11

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Gustafsson, OscarWanhammar, Lars

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