Extended results for minimum-adder constant integer multipliers
2002 (English)In: IEEE International Symposium on Circuits and Systems,2002, Piscataway, NJ: IEEE , 2002, I/73- p.Conference paper (Refereed)
By introducing simplifications to multiplier graphs we extend the previous work on minimum adder multipliers to five adders and show that this is enough to express all coefficients up to 19 bits. The average savings are more than 25% for 19 bits compared with CSD multipliers. The simplifications include addition reordering and vertex reduction to see that different graphs can generate the same coefficient sets. Thus, fewer graphs need to be evaluated. A classification of the graphs reduces the effort to search the coefficient space further.
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2002. I/73- p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34601DOI: 10.1109/ISCAS.2002.1009780Local ID: 22204OAI: oai:DiVA.org:liu-34601DiVA: diva2:255449