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Trade-offs in multiplier block algorithms for low power digit-serial FIR filters
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.ORCID iD: 0000-0003-3470-3911
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
2006 (English)In: WSEAS Int. Conf. Circuits,2006, Athens: WSEAS , 2006Conference paper, Published paper (Refereed)
Abstract [en]

In this paper trade-offs in digit-serial multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity and adder depth. Among the three algorithms is a new algorithm that reduces the number of shifts while the number of adders is on average the same. Hence, the total complexity is reduced for multiplier blocks implemented using digit-serial arithmetic, where shift operations have a hardware cost. An example implementation is used to compare the power consumption for five approaches: the three algorithms, using separate multipliers based on CSD representation, and an algorithm based on subexpression sharing. The design of low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main factor that needs to be considered is adder depth. Furthermore, digit-serial shifts will reduce glitch propagation.

Place, publisher, year, edition, pages
Athens: WSEAS , 2006.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34744Local ID: 23050OAI: oai:DiVA.org:liu-34744DiVA: diva2:255592
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-03-11

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http://www.es.isy.liu.se/publications/papers_and_reports/2006/CSCC06_kennyj_serial_MB.pdf

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Johansson, KennyGustafsson, OscarWanhammar, Lars

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