Multiple Constant Multiplication for Digit-Serial Implementation of Low Power FIR Filters
2006 (English)In: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, no 7, 1001-1008 p.Article in journal (Refereed) Published
Multiple constant multiplication (MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. By utilizing redundancy between the coefficients the number of adders and subtracters is reduced resulting in a low complexity implementation. However, for digit-serial arithmetic a shift requires a flip-flop, and, hence, the number of shifts should be taken into consideration as well. In this work we investigate the area, speed, power trade-offs for implementation of FIR filters using MCM and digit-serial arithmetic. We also introduce an algorithm for reducing both the number of adders and subtracters as well as the number of shifts.
Place, publisher, year, edition, pages
2006. Vol. 5, no 7, 1001-1008 p.
Multiple constant multiplication, Multiplier block, Multiplierless, Digit-serial arithmetic, FIR filter, Low power, Adder graph, Shift-and-add multiplication, Adder depth
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34745Local ID: 23051OAI: oai:DiVA.org:liu-34745DiVA: diva2:255593