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A 4.5 GHz 130nm 32-kb LO cache with a leakage-tolerant self reverse-bias bitline scheme.
Intel Corp., Hillsboro, USA.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
Intel Corp., Hillsboro, USA.
Intel Corp., Hillsboro, USA.
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2003 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no No. 5, 755-761 p.Article in journal (Refereed) Published
Place, publisher, year, edition, pages
2003. Vol. 38, no No. 5, 755-761 p.
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Engineering and Technology
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URN: urn:nbn:se:liu:diva-34758Local ID: 23130OAI: oai:DiVA.org:liu-34758DiVA: diva2:255606
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-12-13

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Alvandpour, Atila

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