Noise analysis of downcenversion sampling mixer
2003 (English)In: Proceedings of the European Conference on Circuit Theory and Design (ECCTD), 2003, 181-184 p.Conference paper (Refereed)
In this paper we address noise properties of an RF downconversion sampling mixer. The relevant noise mechanisms in a SIH circuit are reviewed and investigated. The jitter-induced noise that originates from the sampling clock and the switch driver is shown to be critical in the RF front-end application. Some practical design ideas aimed at optimization of the circuit parameters and the sampling frequency are included. The noise analysis is verified experimentally with a CMOS test chip intended for RF signals up to 2 GHz. The circuit structure and the relevant measurement setup are presented. The obtained results validate our noise analysis.
Place, publisher, year, edition, pages
2003. 181-184 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34776Local ID: 23198OAI: oai:DiVA.org:liu-34776DiVA: diva2:255624
ECCTD '03, The 16th European Conference on Circuit Theory and Design, 1 - 4 September 2003, Kraków, Poland