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Expandable high throughput vector based access memory architecture
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2002 (English)In: Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002, Bologna: University of Bologna , 2002, 599-602 p.Conference paper, Published paper (Refereed)
Abstract [en]

New memory architecture with improved performance in term of expandability and throughput was developed. The architecture, primarily developed for vector access based RF-applications and demonstrated in an electronic warfare application, has potential for closely related applications like cash memories and network routers. A prototype chip with a 64-kbit four-port memory on chip and distributed control logic was designed and fabricated in a standard 0.8 µm BiCMOS process (1M transistors). The research design goal was 10 Gbit/s throughput, using 8 bit data streams and 320 MHz operation frequency. Measurements on prototype chip confirmed the design goal to 50% (5 Gbit/s).

Place, publisher, year, edition, pages
Bologna: University of Bologna , 2002. 599-602 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34838Local ID: 23613OAI: oai:DiVA.org:liu-34838DiVA: diva2:255686
Conference
28th European Solid-State Circuits Conference, September 24 - 26 2002, Firenze, Italy
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-02-13
In thesis
1. CMOS circuits for digital RF systems
Open this publication in new window or tab >>CMOS circuits for digital RF systems
2002 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes some high performance CMOS circuits and architectures developed for digital signal processing of Radio Frequency (RF) signals. Experimental results are demonstrated in a generic radar jammer architecture.

The goal is to reach high performance RF system designs utilizing the continuous development of standard commercial CMOS processes. This is done using a comprehensive view with focus on three levels, circuits, devices and architectures. Finally these levels are joined in a system on chip (SoC).

At circuit level a new clocking strategy, the true single-phase-clock (TSPC) dynamic CMOS circuit technique, was introduced. TSPC is based on a single clock wire, which simplifies the clock distribution and give higher performance compared to earlier two and four wire solutions. Chips has been designed and fabricated to verify TSPC.

At device level two chips has been developed, fabricated and verified. First a single chip Digital Radio Frequency Memory (DRFM) with analog output containing digital parts and on chip D/A converter. Then a single chip Direct Digital Frequency Synthesizer (DDFS) with on chip D/A converters for four-phase analog output. Calculated sine and cosine values are based on ROM tables and interpolation. Both devices utilize TSPC to reach high performance and are frequently used in radar jammers, DRFM for storage of radar pulses and DDFS for frequency selection.

At architecture level the material covers three areas: Globally Updated Mesochronous Design Style (GUM-design-style), Expandable High Throughput Vector Based Access Memory Architecture, and Event Driven Data Processing Architecture.

GUM-design-style reduces the design effort needed in large high performance synchronous digital designs by early functional partitioning and identification of all needed high speed digital signal links between partitions in the system. Each function is then developed individually which reduces its complexity and by that its design effort needed. Global synchronism is obtained after integration by a calibration procedure.

Expandable High Throughput Vector Based Access Memory Architecture improves performance in terms of expandability and throughput for vector access compared to standard memories. Each memory chip has two high-speed data ports used only for connections to adjacent chip. One for connection upward, to device accessing information or a memory chip, the other for connection downward to another memory chip. Expandability is based on mentioned cascade coupling of chips and distributed control function. Memory content is accessed given start point and length of a vector, if the vector is stored on several chips then a distributed internal controller handle the internal management between the chips.

Finally, Event Driven Data Processing Architecture increases reconfigurable real-time system performance by extension of traditional programmable computing architecture, software and hardware, to express and execute event and time operations. The architecture is demonstrated in a real-time RF processing radar application.

All architectures have been used in chip design, and results verified by measurements.

Place, publisher, year, edition, pages
Linköping: Linköping studies in science and technology., 2002. 16 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 775
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34861 (URN)23738 (Local ID)91-7373-429-2 (ISBN)23738 (Archive number)23738 (OAI)
Public defence
2002-10-25, Sal Visionen, Linköpings Universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-02-13

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Söderquist, Ingemar

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