Expandable high throughput vector based access memory architecture
2002 (English)In: Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002, Bologna: University of Bologna , 2002, 599-602 p.Conference paper (Refereed)
New memory architecture with improved performance in term of expandability and throughput was developed. The architecture, primarily developed for vector access based RF-applications and demonstrated in an electronic warfare application, has potential for closely related applications like cash memories and network routers. A prototype chip with a 64-kbit four-port memory on chip and distributed control logic was designed and fabricated in a standard 0.8 µm BiCMOS process (1M transistors). The research design goal was 10 Gbit/s throughput, using 8 bit data streams and 320 MHz operation frequency. Measurements on prototype chip confirmed the design goal to 50% (5 Gbit/s).
Place, publisher, year, edition, pages
Bologna: University of Bologna , 2002. 599-602 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34838Local ID: 23613OAI: oai:DiVA.org:liu-34838DiVA: diva2:255686
28th European Solid-State Circuits Conference, September 24 - 26 2002, Firenze, Italy