liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Speed study of a 2,5 Gb/s equalizer for optical communication in a 3 V 0.35 μm CMOS process
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2002 (English)In: Proc. 2002 20th NORCHIP conference, Piscataway: IEEE , 2002Conference paper, Published paper (Refereed)
Abstract [en]

Decision feedback equalizers, DFE, can be used to increase the data rate of a fiber-optic communication system when intersymbol interference is a problem. The DFE must itself be fast to handle high bit rates. One way to manage high speed, is to introduce parallelism or interleaving. Requirements for the recovering time for the comparators and speed of memory cells will than decrease.

Place, publisher, year, edition, pages
Piscataway: IEEE , 2002.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34839Local ID: 23630OAI: oai:DiVA.org:liu-34839DiVA: diva2:255687
Conference
20th IEEE NORCHIP Conference, Copenhagen, Denmark, November 11-12, 2002
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-01-25
In thesis
1. High speed CMOS optical receiver
Open this publication in new window or tab >>High speed CMOS optical receiver
2004 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Optical communication develops very fast and is today the main method for long distance wired communication. However cost is still high. Looking back to the evolution of optical transmission systems, one main objective of system development has become more and more important; minimize cost per gigabytes per second per kilometre, Gb/s/km. One possible solution is to utilize cost effective CMOS technology for all electronic parts and replace optical dispersion compensation with electronic equalization. Recent research indicates that deep submicron CMOS technology indeed can be used for realizing highly integrated optical receivers at data rates of tens of gigabit per second. Recent research also shows that expensive optical dispersion compensators can be replaced with electrical equalizers.

This thesis describes an optical receiver in CMOS. The optical receiver consists of a differential transimpedance amplifier, a differential and four times interleaved decision feedback equalizer, DFE coefficient update unit and symbol synchronization. The objective of the thesis is to find a scalable optical receiver topology for high speed, wide input range, low power supply sensitivity and reasonable input related noise, for a CMOS technology with a relative low fT The target is to reach 2.5 Gb/s in a 3.3 V 0.35μm CMOS process. Due to the risk for instability for cascaded broadband amplifiers, the amplifier stability related to the power supply impedance is also investigated

Measurements on the differential transimpedance amplifier show 72 dBΩ transimpedance gain and 1.4 GHz bandwidth. Eye diagrams at data rate of 2.5 Gb/s show a dynamic range of more than 60 dB. The performance is reached with a three-stage transimpedance amplifier, utilizing differential high-speed stages and carefully chosen peaking frequencies.

By measurements on the equalizer, a 2 Gb/s NRZ pattern are sent through a 5 m coaxial cable with an 8 cm open stub for echo generation. The coaxial cable with the stub introduces such large intersymbol interference that there is no eye opening left. The equalizer recovers then the sent data correctly.

The equalizer is clocked with a DLL, which is separately tested. The DLL has a new type of delay cell with low power supply sensitivity. The delay range is 0.31 ns to 21.8 ns. For 0.5 ns delay of a 500 MHz signal, the delay increases 2.5 % if the power supply is decreased from 3.3 V to 3 V.

The DFE coefficient update unit and the symbol synchronization is implemented in verilog-A and verified with simulations.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2004. 94 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 904
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22637 (URN)1921 (Local ID)91-85295-61-2 (ISBN)1921 (Archive number)1921 (OAI)
Public defence
2004-11-12, Sal Visionen, Linköpings universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-01-25

Open Access in DiVA

No full text

Authority records BETA

Bengtson, HåkanSvensson, Christer

Search in DiVA

By author/editor
Bengtson, HåkanSvensson, Christer
By organisation
Electronic DevicesThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 114 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf