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A 1 GHz linearized CMOS track-and-hold circuit
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2002 (English)In: IEEE International Symposium on Circuits and Systems, 2002: ISCAS 2002, 2002, 577-580 p.Conference paper, Published paper (Refereed)
Abstract [en]

A simple solution for linearization of the MOS sampling switch is proposed. It improves the SFDR of a T/H circuit and is suitable for high-speed applications. Sampling at a constant gate-source voltage minimizes sampling errors due to variable MOS sampling switch ON-conductance and channel charge injection, and also eliminates input-dependent sampling instant variation. The proposed linearized T/H circuit is fabricated in a 0.35-μm CMOS process. Test measurements show the sampling of a 1 GHz signal.

Place, publisher, year, edition, pages
2002. 577-580 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34846Local ID: 23650ISBN: 0-7803-7448-7 (print)OAI: oai:DiVA.org:liu-34846DiVA: diva2:255694
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, 26-29 May 2002
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-12-18
In thesis
1. Direct RF sampling receivers for wireless systems in CMOS technology
Open this publication in new window or tab >>Direct RF sampling receivers for wireless systems in CMOS technology
2004 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The fast development of wireless communication systems asks for more flexible and more cost-effective radio architectures. A long term goal is a software defined radio, where communication standards are chosen by reconfiguration of hardware. Direct analog-to-digital conversion of the radio frequency (RF) signal is considered unrealistic due to too high requirements on the analog-to-digital converter. This motivates a need for a highly flexible analog front-end that can be fully integrated in a low cost complementary metal-oxide-semiconductor (CMOS) technology.

This thesis exploits the possibility to utilize switched-capacitor (SC) technique for front-end sampling, downconversion, filtering, and decimation. As a result, a new integrable radio receiver front-end architecture is proposed, based on an RF sampling downconversion (RFSD) filter as a discrete-time multi-functional block in SC technique. The front-end architecture is intended for wireless local area network (WLAN) applications in the 2.4 GHz frequency band. A test chip of the RFSD filter has been fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable bandpass filtering, downconversion to baseband, and decimation of the sampling rate. The RFSD filter full functionality has been achieved for input sampling rates up to 1 072 MS/s. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels and possibly different bands.

A MOS switch linearization method for a track-and-hold (T/H) circuit is also described in the thesis. This method has been verified with a test chip in a 0.35-μm CMOS technology. The test chip measurement results demonstrate about 5 dB lower harmonic distortion in comparison to an ordinary T/H circuit. Based on the proposed linearization method, a down-conversion sampling mixer has been designed in a 0.35-μm CMOS process. lt has an input-referred third-order intercept point of +22 dBm for a 1.6 GHz input signal, measured at a sampling rate of 1.55 GS/s. The downconversion sampling mixer noise properties are investigated by a noise analysis. The noise analysis is validated by measurement results, which show that the jitter-induced noise is critical for low sampling rates. The downconversion sampling mixer is also proved to be applicable for WCDMA and DECT wireless communication standards in a wideband low intermediate frequency receiver architecture.

To sum up, the presented CMOS sampling receiver front-end is suitable to realize a flexible and highly integrable low cost radio architecture.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2004. 62 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 881
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22634 (URN)1917 (Local ID)9173739650 (ISBN)1917 (Archive number)1917 (OAI)
Public defence
2004-07-01, Sal Visionen, Linköping Universitet, Linköping, 13:15 (Swedish)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2017-12-15
2. Signal readout and sampling in CMOS
Open this publication in new window or tab >>Signal readout and sampling in CMOS
2002 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Advances in CMOS technology have resulted in high-performance and low-cost consumer electronics. One of the main driving forces in this progress is technology scaling. The development of integrated circuits is continuously moving to a system-on-chip realization. where the digital signal processing is integrated with analog and mixed-signal circuits. Designing a system-on-chip, architecture choice is important. Another issue is the high-performance analog-to-digital converter, which is often a bottleneck in the system-on-chip design.

An overview of the analog-to-digital conversion performance roadmap and possible applications is given in this licentiate thesis. A high-speed track-and-hold circuit is analyzed as a critical block in the analog-to-digital converter. The main sampling circuit nonidealities and limiting factors are formulated. Several solutions to improve the track-and-hold circuit performance are proposed. To verify the proposed ideas, test chips in 0.35-μm CMOS technology are designed and fabricated. The basic measurement methods are discussed to characterize the high-speed track and-hold circuit performance.

As an application of the analog-to-digital conversion, different receiver architectures are described and compared. The homodyne and the direct analog-to-digital conversion receiver architectures are found to be the most suitable ones for system-on-chip implementation. A new receiver architecture, which utilizes direct sampling at RF, is proposed. An improved high-speed sampling circuit is used in this architecture together with time-interleaved analog-to-digital conversion. The GSM-1800 specification is chosen as target.

Different readout architectures for uncooled IR detection are also described in this thesis. First, an introduction to the infrared detection and readout principles is presented. Next, the readout architectures are compared, considering different degrees of parallelism. The design parameters are optirnized to have the lowest noise equivalent temperature difference (NETD) and the power consumption is chosen to be equal in all readout architectures. The pixelwise architecture is found to have the lowest NETD and the most reasonable design parameters when a realistic noise model is considered.

To summarize the main contributions of this thesis, they are as follows: comparison of readout architectures for uncooled IR detector arrays; a MOS switch linearization method for high-speed sampling is proposed; a sampling error minimization method by using a differential clock is described; a radio architecture with an RF sampling receiver is proposed.

Place, publisher, year, edition, pages
Linköping: Linköping studies in science and technology, 2002. 26 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 967
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34862 (URN)23739 (Local ID)23739 (Archive number)23739 (OAI)
Presentation
2002-09-02, Sal Algoritmen, Linköpings universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-12-14

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