A 1 GHz linearized CMOS track-and-hold circuit
2002 (English)In: IEEE International Symposium on Circuits and Systems, 2002: ISCAS 2002, 2002, 577-580 p.Conference paper (Refereed)
A simple solution for linearization of the MOS sampling switch is proposed. It improves the SFDR of a T/H circuit and is suitable for high-speed applications. Sampling at a constant gate-source voltage minimizes sampling errors due to variable MOS sampling switch ON-conductance and channel charge injection, and also eliminates input-dependent sampling instant variation. The proposed linearized T/H circuit is fabricated in a 0.35-μm CMOS process. Test measurements show the sampling of a 1 GHz signal.
Place, publisher, year, edition, pages
2002. 577-580 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34846Local ID: 23650ISBN: 0-7803-7448-7OAI: oai:DiVA.org:liu-34846DiVA: diva2:255694
IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, 26-29 May 2002