An RF sampling front-end for a digital receiver
2002 (English)In: Proceedings of the 20th IEEE NORCHIP Conference, Copenhagen: TechnoData A/S , 2002, 21-26 p.Conference paper (Refereed)
An RF sampling front-end is presented in this paper. The front-end specifications are defined using the GSM-1800 requirements. The implementation of the front-end has been concentrated on a sampler, which is expected to be the most critical block. A linearized sampler is proposed to achieve the high linearity specifications. The sampler enables sampling of a wide band signal at high frequencies. lt is designed in 0.35-μm CMOS process. The simulation results proves, that the sampler achieves high linearity up to carrier frequency. To clock the linearized sampler a low-jitter clock path is presented. lt reduces the clock path sensitivity to power supply variations and protects the clock from additional on-chip jitter.
Place, publisher, year, edition, pages
Copenhagen: TechnoData A/S , 2002. 21-26 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-34847Local ID: 23651OAI: oai:DiVA.org:liu-34847DiVA: diva2:255695
20th IEEE NORCHIP Conference, Copenhagen, Denmark, November 11-12, 2002