This thesis is about digitally controlled analog multiplier-accumulator (MAC) units and their utilization in communications applications. These units are implemented as switched-capacitor circuits, designed with switches (MOS transistors), capacitors (MOS transistors), and amplifiers (MOS transistors); using a CMOS technology. The switched-capacitor technique is a mean for analog discretetime signal processing where charges representing signal values are transported between capacitors of different sizes and by that implementing multiplicative and additive computations.
These analog MAC units are suggested as signal processing engines in radio receivers; where they sample an intermediate-frequency radio waveform and weights individually samples with digitally controlled coefficients. One example of such an application is a programmable finite-duration impulse response (FIR) filter combined with decimation, where the bandwidth and center frequency is controlled by digitally means with virtually constant number of MAC units operating in parallel. However, non-finite amplifier gain in the switch-capacitance circuits give rise to an accumulation loss, which limits the useful FIR filter length. This accumulation may in some respect be compensated for in advance when the coefficient sequence is known. A simulation on a 399-tap FIR filter executed with signed 8-bit MAC units shows that the expected ultimate rejection is 65dB and true filter gain 38dB. Two types of FIR filters with decimation are suggested; quadrature FIR filters which computes the quadrature components at a desired input frequency, and low-IF filters which computes a band-pass signal at a desired input frequency.
When comparing two equivalent mixed analog/digital systems implementations; an all-digital system featured by a front-end ND converter followed by digital MAC units, versus a sampled-analog system with front-end analog MAC units followed by an AID converter, the later wins in lowpower due to a relaxed requirement on the AID converter with applications where signal processing tasks are computed as the linear combination of input samples and digital coefficients. This is typical for systems where the input bandwidth is much larger then the desired bandwidth, such as radio environments. Hence, a motive for using analog MAC units is low power consumption.
A typical application where the input bandwidth is larger than the desired bandwidth is in direct-sequence spread-spectrum (DS/SS) communications. The utilization of a signed 1-bit analog MAC unit on a fabricated test chip as simultaneous demodulator and despreader for DS/SS communications is demonstrated. From a 2Mchip/s direct-sequence spread quaternary-phase-shift keyed (DS/QPSK) signal waveform with 7 chips per data symbol, the test chip samples and weights the waveform in selected instants chosen according to the spreading code, which is known by the receiver, and accumulate these weighted samples to directly compute data symbol estimates as coordinates in an IQ diagram. With an input signal of 120μV effective voltage (-65dBm over 50Ω load) the signal- to-noise ratio ofthe detected data symbols is 23dB, which leads to the noise figure 16dB.
In another demonstration, a signed 8-bit analog MAC test chip is utilized as a combined channel-select filter and demodulator. The center frequency of this filter is adjustable with a fixed sampling frequency. With a 357kSymbol/s QPSK modulated waveform with carrier frequency 1.43MHz, 2.5MHz, or 3.57MHz and power -61dBm, the test chip compute data symbol estimates as coordinates in an IQ diagram with a measured signal-to-noise ratio of 20dB. The ultimate rejection of these filters is measured to 25dB, and the noise figure is 29dB.
Linköping: Linköping studies in science and technology , 2002. , 38 p.
2002-12-10, Sal Visionen, Linköpings Universitet, Linköping, 10:15 (Swedish)