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Digitally controlled analog multiply-accumulate units
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2002 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis is about digitally controlled analog multiplier-accumulator (MAC) units and their utilization in communications applications. These units are implemented as switched-capacitor circuits, designed with switches (MOS transistors), capacitors (MOS transistors), and amplifiers (MOS transistors); using a CMOS technology. The switched-capacitor technique is a mean for analog discretetime signal processing where charges representing signal values are transported between capacitors of different sizes and by that implementing multiplicative and additive computations.

These analog MAC units are suggested as signal processing engines in radio receivers; where they sample an intermediate-frequency radio waveform and weights individually samples with digitally controlled coefficients. One example of such an application is a programmable finite-duration impulse response (FIR) filter combined with decimation, where the bandwidth and center frequency is controlled by digitally means with virtually constant number of MAC units operating in parallel. However, non-finite amplifier gain in the switch-capacitance circuits give rise to an accumulation loss, which limits the useful FIR filter length. This accumulation may in some respect be compensated for in advance when the coefficient sequence is known. A simulation on a 399-tap FIR filter executed with signed 8-bit MAC units shows that the expected ultimate rejection is 65dB and true filter gain 38dB. Two types of FIR filters with decimation are suggested; quadrature FIR filters which computes the quadrature components at a desired input frequency, and low-IF filters which computes a band-pass signal at a desired input frequency.

When comparing two equivalent mixed analog/digital systems implementations; an all-digital system featured by a front-end ND converter followed by digital MAC units, versus a sampled-analog system with front-end analog MAC units followed by an AID converter, the later wins in lowpower due to a relaxed requirement on the AID converter with applications where signal processing tasks are computed as the linear combination of input samples and digital coefficients. This is typical for systems where the input bandwidth is much larger then the desired bandwidth, such as radio environments. Hence, a motive for using analog MAC units is low power consumption.

A typical application where the input bandwidth is larger than the desired bandwidth is in direct-sequence spread-spectrum (DS/SS) communications. The utilization of a signed 1-bit analog MAC unit on a fabricated test chip as simultaneous demodulator and despreader for DS/SS communications is demonstrated. From a 2Mchip/s direct-sequence spread quaternary-phase-shift keyed (DS/QPSK) signal waveform with 7 chips per data symbol, the test chip samples and weights the waveform in selected instants chosen according to the spreading code, which is known by the receiver, and accumulate these weighted samples to directly compute data symbol estimates as coordinates in an IQ diagram. With an input signal of 120μV effective voltage (-65dBm over 50Ω load) the signal- to-noise ratio ofthe detected data symbols is 23dB, which leads to the noise figure 16dB.

In another demonstration, a signed 8-bit analog MAC test chip is utilized as a combined channel-select filter and demodulator. The center frequency of this filter is adjustable with a fixed sampling frequency. With a 357kSymbol/s QPSK modulated waveform with carrier frequency 1.43MHz, 2.5MHz, or 3.57MHz and power -61dBm, the test chip compute data symbol estimates as coordinates in an IQ diagram with a measured signal-to-noise ratio of 20dB. The ultimate rejection of these filters is measured to 25dB, and the noise figure is 29dB.

Place, publisher, year, edition, pages
Linköping: Linköping studies in science and technology , 2002. , 38 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 792
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34859Local ID: 23735ISBN: 91-7373-478-0 (print)OAI: oai:DiVA.org:liu-34859DiVA: diva2:255707
Public defence
2002-12-10, Sal Visionen, Linköpings Universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-01-04
List of papers
1. A novel mixed analog/digital MAC unit implemented with SC technique suitable for fully programmable narrow-band FIR filter applications
Open this publication in new window or tab >>A novel mixed analog/digital MAC unit implemented with SC technique suitable for fully programmable narrow-band FIR filter applications
1999 (English)In: Proceedings of ICECS '99. The 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, 1999, 1197-1200 p.Conference paper, Published paper (Refereed)
Abstract [en]

A mixed analog/digital (MAD) multiply-accumulate (MAC) unit, implemented with switched-capacitor (SC) technique is presented. The MAC unit consist of a programmable capacitor array (PCA) for coefficient representation, and an integrator for accumulation. A coefficient compensation technique to neutralize the non-ideal MAC properties due to finite opamp gain is introduced. The MAD-MAC unit is a new concept for effective mapping of signal processing tasks on SC technique; in particular high-order fully programmable narrow-band FIR filter applications. The utilization of the MAD-MAC unit concept is shown with a simulation of a decimated 400-tap narrow-band FIR filter

Keyword
Band pass filters, Circuits, Complexity theory, Delay, Finite impulse response filter, Flow graphs, Frequency, Narrowband, Nonlinear filters, Physics
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-86792 (URN)10.1109/ICECS.1999.814384 (DOI)0-7803-5682-9 (ISBN)
Conference
The 6th IEEE International Conference on Electronics, Circuits and Systems, 5-8 September, Pafos, Cyprys, 1999
Available from: 2013-01-04 Created: 2013-01-04 Last updated: 2013-01-04
2. Realization of fully programmable narrow-band FIR filters with SC technique
Open this publication in new window or tab >>Realization of fully programmable narrow-band FIR filters with SC technique
1999 (English)In: 42nd Midwest Symposium on Circuits and Systems, 1999, 1999, 464-468 p.Conference paper, Published paper (Refereed)
Abstract [en]

A methodology to implement fully programmable narrow-band FIR filters with switched capacitor (SC) technique is presented. The SC implementation, which offers a fixed order of complexity, is suitable for high-order FIR filter realizations followed by decimation. The filter performance and the requirements are analyzed

Keyword
Capacitors, Circuits, Convolution, Delay, Digital filters, Finite impulse response filter, Narrowband, Performance analysis, Physics, Signal processing
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-86794 (URN)10.1109/MWSCAS.1999.867305 (DOI)0-7803-5491-5 (ISBN)
Conference
42nd Midwest Symposium on Circuits and Systems, Las Cruces, New Mexico, 8-11 August, 1999
Available from: 2013-01-04 Created: 2013-01-04 Last updated: 2013-01-04
3. Low power mixed analog-digital signal processing
Open this publication in new window or tab >>Low power mixed analog-digital signal processing
2000 (English)In: ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design, New York, USA: Association for Computing Machinery (ACM), 2000, 61-66 p.Conference paper, Published paper (Refereed)
Abstract [en]

The power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and accumulaðtions, is analyzed. An implementation is proposed, composed of switched-capacitor mixed analog/digital multiply accumulate units in the analog front-end, followed by an A/D converter. This impleðmentation is shown to be superior in respect of power consumption compared to an equivalent implementation with a high-speed A/D converter in the front-end, to execute signal processing tasks that include decimation. The power savings are only due to relaxed requirement on A/D conversion rate, as a direct consequence of the decimation. In a case study of a narrowband FIR filter, realized with four multiply accumulate units, and with a decimation factor of 100; power saving is 54 times. Implementation details are given, the power consumption, and the thermal noise are analyzed.

Place, publisher, year, edition, pages
New York, USA: Association for Computing Machinery (ACM), 2000
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-86795 (URN)10.1145/344166.344201 (DOI)1-58113-190-9 (ISBN)
Conference
2000 International Symposium on Low Power Electronics and Design, ISLPED '00, Rapallo, Italy, July 25-27, 2000
Available from: 2013-01-04 Created: 2013-01-04 Last updated: 2015-01-30
4. A study of the non-ideal properties of sample-and-hold circuits with respect to the analog bandwidth
Open this publication in new window or tab >>A study of the non-ideal properties of sample-and-hold circuits with respect to the analog bandwidth
1999 (English)In: Proc. of 3rd IEE Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications, 1999, 119-121 p.Conference paper, Published paper (Refereed)
Abstract [en]

The fast evolving communication market demands decreased fabrication cost, which will be met by highly integrated circuit solutions. In the near future, we will see system-on-a-chip solutions in CMOS technology, where transceivers will be integrated on a single chip preferably, also with digital circuitry. Receiver topologies with A/D conversion at higher frequencies are interesting from an integration point of view. Therefore, a deeper understanding of the A/D converter limitations to cope with high-frequency signals is needed. This paper will highlight the track-and-hold circuit linearity, which is a frequency dependent fundamental limit on the A/D conversion accuracy

Series
IEE Conference Publication Series, ISSN 0537-9989
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-86796 (URN)10.1049/cp:19990478 (DOI)0-85296-718-7 (ISBN)
Conference
Third International Conference on (Conf. Publ. No. 466) Advanced A/D and D/A Conversion Techniques and Their Applications, 27-28 July 1999, Glasgow
Available from: 2013-01-04 Created: 2013-01-04 Last updated: 2013-01-17
5. Analog MAC unit with digital coefficients suitable for IF filtering and demodulation
Open this publication in new window or tab >>Analog MAC unit with digital coefficients suitable for IF filtering and demodulation
(English)Manuscript (preprint) (Other academic)
Abstract [en]

A digitally programmable analog interface for communication applications is presented. The interface consists of a sampler, an analog multiplier, and an analog accumulator; where the analog multiplier features signed 8-bit coefficient resolution. The interface is implemented with switched-capacitor technique and is demonstrated with a test chip, fabricated using a low-cost 0.6)μm CMOS process.The interface is shown to be able to combine a programmable band-pass filter of FIR type with a demodulator for quadrature modulation. The bandwidth and center frequency of this filter is programmable with a fixed clock frequency, which is a useful property in multi-standard receivers. As a demonstration, the interface is controlled, in real-time by digital control stimuli, to act as sampler and combined 27th-order FIR filter and demodulator at three different frequencies; 1.43MHz, 2.50MHz, and 3.57MHz. The test chip clock frequency is fixed to 10MHz. The test chip hence samples, filters, and demodulates a 357kSymbol/s QPSK modulated waveform with carrier frequency 1.43MHz, 2.50MHz, or 3.57MHz, and with power -61dBm. The measured ultimate rejection of the 27th-order FIR filter is measured to 25dB, and the noise figure is measured to 29dB.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-86797 (URN)
Available from: 2013-01-04 Created: 2013-01-04 Last updated: 2013-01-04
6. Sampling and analog despreading of a DS/SS modulated signal directly on the IF waveform
Open this publication in new window or tab >>Sampling and analog despreading of a DS/SS modulated signal directly on the IF waveform
(English)Manuscript (preprint) (Other academic)
Abstract [en]

This paper introduces a method how to interpret the user data directly from a direct-sequence spread quaternary-phase-shift keyed (DS/QPSK) modulated wave-form without first demodulate nor digitize the waveform. The Methos is to sample the waveform, to weight each individual sample with -1, 0, or +1 according to the spreading code, and finally to accumulate these weighted samples. The wave-form carrier frequency is chosen as a multiple of the chop rate. This demonstrated with a 0.6μm CMOS test chip that is fed with a 2Mchip/s DS/QPSK modulated signal, shaped with a Root-Nyquist filter. The measurement result cerifies correct interpreting of transmitted data symbols (user data) represented over seven chips. The test chip further exhibit a measured noise figure 16.2dB at a bandwidth expansion of 7.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-86799 (URN)
Available from: 2013-01-04 Created: 2013-01-04 Last updated: 2013-01-04

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