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CMOS circuits for digital RF systems
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2002 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes some high performance CMOS circuits and architectures developed for digital signal processing of Radio Frequency (RF) signals. Experimental results are demonstrated in a generic radar jammer architecture.

The goal is to reach high performance RF system designs utilizing the continuous development of standard commercial CMOS processes. This is done using a comprehensive view with focus on three levels, circuits, devices and architectures. Finally these levels are joined in a system on chip (SoC).

At circuit level a new clocking strategy, the true single-phase-clock (TSPC) dynamic CMOS circuit technique, was introduced. TSPC is based on a single clock wire, which simplifies the clock distribution and give higher performance compared to earlier two and four wire solutions. Chips has been designed and fabricated to verify TSPC.

At device level two chips has been developed, fabricated and verified. First a single chip Digital Radio Frequency Memory (DRFM) with analog output containing digital parts and on chip D/A converter. Then a single chip Direct Digital Frequency Synthesizer (DDFS) with on chip D/A converters for four-phase analog output. Calculated sine and cosine values are based on ROM tables and interpolation. Both devices utilize TSPC to reach high performance and are frequently used in radar jammers, DRFM for storage of radar pulses and DDFS for frequency selection.

At architecture level the material covers three areas: Globally Updated Mesochronous Design Style (GUM-design-style), Expandable High Throughput Vector Based Access Memory Architecture, and Event Driven Data Processing Architecture.

GUM-design-style reduces the design effort needed in large high performance synchronous digital designs by early functional partitioning and identification of all needed high speed digital signal links between partitions in the system. Each function is then developed individually which reduces its complexity and by that its design effort needed. Global synchronism is obtained after integration by a calibration procedure.

Expandable High Throughput Vector Based Access Memory Architecture improves performance in terms of expandability and throughput for vector access compared to standard memories. Each memory chip has two high-speed data ports used only for connections to adjacent chip. One for connection upward, to device accessing information or a memory chip, the other for connection downward to another memory chip. Expandability is based on mentioned cascade coupling of chips and distributed control function. Memory content is accessed given start point and length of a vector, if the vector is stored on several chips then a distributed internal controller handle the internal management between the chips.

Finally, Event Driven Data Processing Architecture increases reconfigurable real-time system performance by extension of traditional programmable computing architecture, software and hardware, to express and execute event and time operations. The architecture is demonstrated in a real-time RF processing radar application.

All architectures have been used in chip design, and results verified by measurements.

Place, publisher, year, edition, pages
Linköping: Linköping studies in science and technology. , 2002. , 16 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 775
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-34861Local ID: 23738ISBN: 91-7373-429-2 (print)OAI: oai:DiVA.org:liu-34861DiVA: diva2:255709
Public defence
2002-10-25, Sal Visionen, Linköpings Universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-02-13
List of papers
1. A true single-phase-clock dynamic CMOS circuit technique
Open this publication in new window or tab >>A true single-phase-clock dynamic CMOS circuit technique
1987 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 5, no 22, 899-901 p.Article in journal (Refereed) Published
Abstract [en]

The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88613 (URN)10.1109/JSSC.1987.1052831 (DOI)
Available from: 2013-02-13 Created: 2013-02-13 Last updated: 2017-12-06
2. True single phase clock dynamic CMOS circuit technique
Open this publication in new window or tab >>True single phase clock dynamic CMOS circuit technique
1988 (English)In: IEEE International Symposium on Circuits and Systems, 1988, 1988, 475-478 p.Conference paper, Published paper (Refereed)
Abstract [en]

Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3-μm CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88618 (URN)10.1109/ISCAS.1988.14967 (DOI)
Conference
IEEE International Cymposium on Circuits and Systems, Espoo, Finland, 7-9 June 1988
Available from: 2013-02-13 Created: 2013-02-13 Last updated: 2013-02-13
3. A 200 MHz CMOS digital radio frequency memory chip with analog output
Open this publication in new window or tab >>A 200 MHz CMOS digital radio frequency memory chip with analog output
1993 (English)In: Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, 1993, 16.3.1-16.3.4 p.Conference paper, Published paper (Refereed)
Abstract [en]

A single-chip architecture which realizes most of the intermediate-frequency (IF) part of a digital radio frequency memory (DRFM) is presented. The implementation in CMOS technology (Lnom = 1 μm), called the DRFMC, allows different modes of operation with 200-MHz clock frequency (400-MHz nominal). The modes are pulsed signal synthesis, delay line, or continuous-wave (CW) synthesis. The DRFMC is programmable via a DMA interface. A digital signal processing unit and a digital-to-analog converter have been included. The output is analog and digital, which supports cascading of several DRFMCs

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88622 (URN)10.1109/CICC.1993.590731 (DOI)0-7803-0826-3 (ISBN)
Conference
IEEE 1993 Custom Integrated Circuits Conference (CICC '93), May 9-12 1993, San Diego, California
Available from: 2013-02-13 Created: 2013-02-13 Last updated: 2013-02-13
4. A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters
Open this publication in new window or tab >>A 0.8 μm CMOS 350 MHz quadrature direct digital frequency synthesizer with integrated D/A converters
1998 (English)In: 1998 Symposium on VLSI Circuits, 1998. Digest of Technical Papers, 1998, 54-55 p.Conference paper, Published paper (Refereed)
Abstract [en]

This quadrature DDFS calculates sine and cosine values with a tuning resolution below 1 Hz, by only using an 8 word ROM and interpolation. Two internal 8-bit differential D/A converters generate the four-phase analog output signal. A spurious free dynamic range of 50 dB for low frequencies and 30 dB near Nyquist is achieved.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88624 (URN)10.1109/VLSIC.1998.688001 (DOI)0-7803-4766-8 (ISBN)
Conference
1998 Symposium on VLSI circuits, Honolulu, Hawaii, June 11-13 1998
Available from: 2013-02-13 Created: 2013-02-13 Last updated: 2013-02-13
5. Globally updated mesochronous design style (GUM-design-style)
Open this publication in new window or tab >>Globally updated mesochronous design style (GUM-design-style)
2002 (English)In: Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002, Bologna: University of Bologna , 2002, 603-606 p.Conference paper, Published paper (Refereed)
Abstract [en]

In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure do to metastability. Synchronous design style is widely used, easy to grasp and to implement, also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous design style (GUM-design-style) is to overcome those by identifying and allowing all single and bidirectional high-speed signal links needed, still retaining the simplicity uncomplicated implementation and tool support. In this paper GUM-design-style is described, analysed and demonstrated. Experimental results from a large-scale high-speed system using three 0.8 µm BiCMOS chips are given. GUM-design-style is scaleable and suitable for future System on Chip (SoC) both on and between chips.

Place, publisher, year, edition, pages
Bologna: University of Bologna, 2002
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34836 (URN)23611 (Local ID)23611 (Archive number)23611 (OAI)
Conference
28th European Solid-State Circuits Conference, September 24 - 26 2002, Firenze, Italy
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-02-13
6. Expandable high throughput vector based access memory architecture
Open this publication in new window or tab >>Expandable high throughput vector based access memory architecture
2002 (English)In: Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002, Bologna: University of Bologna , 2002, 599-602 p.Conference paper, Published paper (Refereed)
Abstract [en]

New memory architecture with improved performance in term of expandability and throughput was developed. The architecture, primarily developed for vector access based RF-applications and demonstrated in an electronic warfare application, has potential for closely related applications like cash memories and network routers. A prototype chip with a 64-kbit four-port memory on chip and distributed control logic was designed and fabricated in a standard 0.8 µm BiCMOS process (1M transistors). The research design goal was 10 Gbit/s throughput, using 8 bit data streams and 320 MHz operation frequency. Measurements on prototype chip confirmed the design goal to 50% (5 Gbit/s).

Place, publisher, year, edition, pages
Bologna: University of Bologna, 2002
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34838 (URN)23613 (Local ID)23613 (Archive number)23613 (OAI)
Conference
28th European Solid-State Circuits Conference, September 24 - 26 2002, Firenze, Italy
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-02-13
7. Event driven data processing architecture applied to reconfigurable digital RF system
Open this publication in new window or tab >>Event driven data processing architecture applied to reconfigurable digital RF system
(English)Manuscript (preprint) (Other academic)
Abstract [en]

This paper describes a data processing architecture where events and time are in focus. This differs from traditional von Neumann and data flow architectures. Also function and performance are closely handled at all levels of description, implementation and execution. New instruction codes are defined and special circuitry is introduced to express and execute event and time operations. This results in reconfigurable software controlled functionality together with real-time performance close to a dedicated VLSI solution. The architecture is demonstrated in a real-time RF processing radar application and its theory, design, implementation, simulation and testing is presented. A prototype chip, complete with 32-kbyte signal memory, 2-kbyte instruction memory, four processing units in parallel and interfaces for digitized RF signals and host computer, is fabricated in 0.35 μm standard CMOS. Time events of signal data on two simultaneous 8 bit links can be controlled with a time resolution of one clock period. Measurements verified conect function and performance above 400 MHz clock frequency at 3.3 Volt supply. Power consumption is 3.6-Watt @320 MHz.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88627 (URN)
Available from: 2013-02-13 Created: 2013-02-13 Last updated: 2013-02-13

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